def __init__(self):
self.pwd = os.path.dirname(os.path.abspath(__file__))
self.rtl = os.path.join(self.pwd, '../src/rtl/')
self.tst = os.path.join(self.pwd, '../tests/')
self.work = vhdlScript()
def addSrc(self, work):
work.addSrc(self.rtl)
def addTst(self, work):
work.addTstConfigFile(self.tst)
def add(self, work):
self.addSrc(work)
self.addTst(work)
if __name__ == "__main__":
# Init ALU
tstUla = tstUla()
# Logica Combinacional RTL
tstLogiComb = tstLogiComb()
tstLogiComb.addSrc(tstUla.work)
logLogiComb("---------- Portas Logicas ")
logLogiComb("---------- 04-Unidade-Logica-Aritmetica")
tstUla.add(tstUla.work)
tstUla.work.run()
self.work = vhdlScript()
def addSrc(self, work):
work.addSrc(self.rtl)
def addTst(self, work):
work.addTstConfigFile(self.tst)
def add(self, work):
self.addSrc(work)
self.addTst(work)
if __name__ == "__main__":
# Init ALU
tstLogiSeq = tstLogiSeq()
# Logica Combinacional RTL
tstLogiComb = tstLogiComb()
tstLogiComb.addSrc(tstLogiSeq.work)
# ULA
tstUla = tstUla()
tstUla.addSrc(tstLogiSeq.work)
# Logica Sequencial
logLogiComb("---------- E-Logica-Sequencial")
tstLogiSeq.add(tstLogiSeq.work)
tstLogiSeq.work.run()
def print(self):
logLogiComb("---------- Portas Logicas ")
logLogiComb("---------- 03-Logica-Combinacional ")