def my_test():
sim = logsim.Sim()
def setv(wires, value):
for i, w in enumerate(wires):
sim.initialize(w, (value >> i) & 1)
inM, instruction, reset = wires(16), wires(16), Wire()
outM, writeM, addressM, pc = CPU(inM, instruction, reset, sim)
sim.watch(instruction, 'instruction')
sim.watch(outM, 'outM')
sim.watch(writeM, 'writeM')
sim.watch(addressM, 'addressM')
sim.watch(pc, 'pc')
sim.initialize(reset, 1)
setv(inM, 0)
setv(instruction, 0)
sim.tick(); sim.tock()
sim.time = 0
sim.initialize(reset, 0)
setv(instruction, int('0011000000111001', 2))
sim.tick(); sim.tock()
sim.tick(); sim.tock()
def test_mux4way16():
a = wires(16)
b = wires(16)
c = wires(16)
d = wires(16)
sel = wires(2)
out = mux4way16(a, b, c, d, sel)
simtest.test(locals(), 'tests/1/Mux4Way16.tst')
def test_mux8way16():
a = wires(16)
b = wires(16)
c = wires(16)
d = wires(16)
e = wires(16)
f = wires(16)
g = wires(16)
h = wires(16)
sel = wires(3)
out = mux8way16(a, b, c, d, e, f, g, h, sel)
simtest.test(locals(), 'tests/1/Mux8Way16.tst')
def test_CPU():
inM, instruction, reset = wires(16), wires(16), Wire()
outM, writeM, addressM, pc = CPU(inM, instruction, reset)
simtest.test(locals(), 'tests/5/CPU.tst')
def test_alu():
x, y = wires(16), wires(16)
zx, nx, zy, ny, f, no = wires(6)
out, zr, ng = alu(x, y, zx, nx, zy, ny, f, no)
simtest.test(locals(), 'tests/2/ALU.tst')
def test_inc16():
in_ = wires(16)
out = inc16(in_)
simtest.test(locals(), 'tests/2/Inc16.tst')
def test_PC():
in_, load, inc, reset = wires(16), Wire(), Wire(), Wire()
out = PC(in_, load, inc, reset)
simtest.test(locals(), 'tests/3/a/PC.tst')
def test_ram8():
in_, load, address = wires(16), Wire(), wires(3)
out = ram8(in_, load, address)
simtest.test(locals(), 'tests/3/a/RAM8.tst')
def test_bit():
in_, load = wires(2)
out = bit(in_, load)
simtest.test(locals(), 'tests/3/a/Bit.tst')
def test_ram64():
in_, load, address = wires(16), Wire(), wires(6)
out = ram64(in_, load, address)
simtest.test(locals(), 'tests/3/a/RAM64.tst')
def test_dmux4way():
in_ = Wire()
sel = wires(2)
a, b, c, d = dmux4way(in_, sel)
simtest.test(locals(), 'tests/1/DMux4Way.tst')
def test_or8way():
in_ = wires(8)
out = or8way(in_)
simtest.test(locals(), 'tests/1/Or8Way.tst')
def test_mux16():
a = wires(16)
b = wires(16)
sel = Wire()
out = mux16(a, b, sel)
simtest.test(locals(), 'tests/1/Mux16.tst')
def test_register():
in_, load = wires(16), Wire()
out = register(in_, load)
simtest.test(locals(), 'tests/3/a/Register.tst')
def test_dmux8way():
in_ = Wire()
sel = wires(3)
a, b, c, d, e, f, g, h = dmux8way(in_, sel)
simtest.test(locals(), 'tests/1/DMux8Way.tst')
def test_ram8():
in_, load, address = wires(16), Wire(), wires(3)
out = ram8(in_, load, address)
simtest.test(locals(), 'tests/3/a/RAM8.tst')
def test_mux():
a, b = wires(2)
sel = Wire()
out = mux(a, b, sel)
simtest.test(locals(), 'tests/1/Mux.tst')
def test_PC():
in_, load, inc, reset = wires(16), Wire(), Wire(), Wire()
out = PC(in_, load, inc, reset)
simtest.test(locals(), 'tests/3/a/PC.tst')
def test_not16():
in_ = wires(16)
out = not16(in_)
simtest.test(locals(), 'tests/1/Not16.tst')
def test_register():
in_, load = wires(16), Wire()
out = register(in_, load)
simtest.test(locals(), 'tests/3/a/Register.tst')
def test_and16():
a = wires(16)
b = wires(16)
out = and16(a, b)
simtest.test(locals(), 'tests/1/And16.tst')
def test_ram64():
in_, load, address = wires(16), Wire(), wires(6)
out = ram64(in_, load, address)
simtest.test(locals(), 'tests/3/a/RAM64.tst')
def test_or16():
a = wires(16)
b = wires(16)
out = or16(a, b)
simtest.test(locals(), 'tests/1/Or16.tst')
def test_full_adder():
a, b, c = wires(3)
sum, carry = full_adder(a, b, c)
simtest.test(locals(), 'tests/2/FullAdder.tst')
def exhaustive_test(spec, builder, ninputs):
inputs = S.wires(ninputs)
outputs = builder(*inputs)
for values in truth_table('x'*ninputs):
#print values, 'spec', spec(*values), 'circuit', run(inputs, values, outputs)
assert spec(*values) == run(values, outputs, inputs)
def test_add16():
a, b = wires(16), wires(16)
out = add16(a, b)
simtest.test(locals(), 'tests/2/Add16.tst')
def test_bit():
in_, load = wires(2)
out = bit(in_, load)
simtest.test(locals(), 'tests/3/a/Bit.tst')
def test_half_adder():
a, b = wires(2)
sum, carry = half_adder(a, b)
simtest.test(locals(), 'tests/2/HalfAdder.tst')
def exhaustive_test(spec, builder, ninputs):
inputs = S.wires(ninputs)
outputs = builder(*inputs)
for values in truth_table('x' * ninputs):
#print values, 'spec', spec(*values), 'circuit', run(inputs, values, outputs)
assert spec(*values) == run(values, outputs, inputs)
