class _Partial(m.Circuit):
nonlocal pi
nonlocal po
reconstructor.run()
pi_to_remove = _add_input_registers(graph, reconstructor)
remove_all(pi, pi_to_remove)
new_pi, new_po = _lift_instance_inputs(reconstructor)
pi += new_pi
po += new_po
io = m.IO(
**{f"I{i}": m.In(type(v.bit.value))
for i, v in enumerate(pi)})
io += m.IO(
**{f"O{i}": m.Out(type(v.bit.value))
for i, v in enumerate(po)})
for i, pii in enumerate(pi):
port = getattr(io, f"I{i}")
bit = reconstructor.get_bit(pii)
bit @= port
for i, pio in enumerate(po):
port = getattr(io, f"O{i}")
bit = reconstructor.get_bit(pio)
port @= bit
name = _name
def __init__(self, length: int, fanout: int = 0):
self.io = m.IO(I=m.In(m.Bit), O=m.Out(m.Bit))
self.io += m.IO(
**{f"fanout_{i}": m.Out(m.Bit)
for i in range(length * fanout)})
index = 0
curr = self.io.I
for _ in range(length):
curr = ~curr
for _ in range(fanout):
out = getattr(self.io, f"fanout_{index}")
out @= curr
index += 1
self.io.O @= curr
class Register(m.Circuit):
name = f"Register_has_ce_{has_ce}_has_reset_{has_reset}_" \
f"has_async_reset_{has_async_reset}_" \
f"has_async_resetn_{has_async_resetn}_" \
f"type_{_type.__name__}_n_{n}"
io = m.IO(I=m.In(T), O=m.Out(T))
io += m.ClockIO(has_ce=has_ce, has_reset=has_reset,
has_async_reset=has_async_reset,
has_async_resetn=has_async_resetn)
reg = DefineCoreirReg(n, init, has_async_reset,
has_async_resetn, _type)(name="value")
I = io.I
O = reg.O
if n is None:
O = O[0]
if has_reset and has_ce:
if reset_priority:
I = mantle.mux([O, I], io.CE, name="enable_mux")
I = mantle.mux([I, m.bits(init, n)], io.RESET)
else:
I = mantle.mux([I, m.bits(init, n)], io.RESET)
I = mantle.mux([O, I], io.CE, name="enable_mux")
elif has_ce:
I = mantle.mux([O, I], io.CE, name="enable_mux")
elif has_reset:
I = mantle.mux([I, m.bits(init, n)], io.RESET)
if n is None:
m.wire(I, reg.I[0])
else:
m.wire(I, reg.I)
m.wire(io.O, O)
def __init__(self, n: int, T: m.Kind = m.Bit, init=None,
has_enable: bool = False,
reset_type: Optional[m.AbstractReset] = None):
if init is None:
init = [T(*_zero_init_args(T)) for _ in range(n)]
self.name = f"SIPO{n}"
self.io = m.IO(
I=m.In(T),
O=m.Out(m.Array[n, T] if T is not m.Bit else m.Bits[n])
)
# TODO: Add magma helper func for this
has_async_reset = reset_type == m.AsyncReset
has_async_resetn = reset_type == m.AsyncResetN
has_reset = reset_type == m.Reset
has_resetn = reset_type == m.ResetN
self.io += m.ClockIO(has_enable=has_enable,
has_async_reset=has_async_reset,
has_async_resetn=has_async_resetn,
has_reset=has_reset, has_resetn=has_resetn)
regs = (m.Register(T, init=init[i], has_enable=has_enable,
reset_type=reset_type)() for i in range(n))
# TODO: Default clock wiring logic raises warning inside scan
self.io.O @= m.scan(regs, scanargs={"I": "O"})(self.io.I)
class mycirc(m.Circuit):
name = 'my_init_cond'
io = m.IO(
va=fault.RealOut,
vb=fault.RealOut,
vc=fault.RealOut
)
class myblk(m.Circuit):
io = m.IO(a=RealIn,
b=RealOut,
c=m.In(m.Bit),
d=m.Out(m.Bits[2]),
e=ElectIn,
f=ElectOut)
class dut(m.Circuit):
name = 'test_gaussian_noise'
io = m.IO(clk=m.ClockIn,
rst=m.BitIn,
mean_in=fault.RealIn,
std_in=fault.RealIn,
real_out=fault.RealOut)
def __init__(self, x_len):
self.io = m.IO(
rs1=m.In(m.UInt[x_len]),
rs2=m.In(m.UInt[x_len]),
br_type=m.In(m.UInt[3]),
taken=m.Out(m.Bit)
)
class dut(m.Circuit):
name = 'test_dff'
io = m.IO(d_i=fault.RealIn,
q_o=fault.RealOut,
rst_i=m.BitIn,
clk_i=m.BitIn,
cke_i=m.BitIn)
class dut(m.Circuit):
name = 'test_table_sim'
io = m.IO(addr=m.In(m.Bits[addr_bits]),
clk=m.In(m.Clock),
real_out=fault.RealOut,
sint_out=m.Out(m.SInt[sint_bits]),
uint_out=m.Out(m.UInt[uint_bits]))
class _CoreirWrapCircuit(magma.Circuit):
name = self.name()
io = magma.IO(**self.decl())
wrapper = Wrapper()
magma.wire(io.I, wrapper.interface.ports["in"])
magma.wire(wrapper.out, io.O)
class Monitor(m.Circuit):
io = m.IO(enq=m.In(m.ReadyValid[T]), deq=m.In(
m.ReadyValid[T])) + m.ClockIO()
m.inline_verilog("""\
reg [7:0] data [0:3];
reg [2:0] write_pointer;
reg [2:0] read_pointer;
wire wen;
wire ren;
wire full;
wire empty;
assign wen = {io.enq.valid} & {io.enq.ready};
assign ren = {io.deq.ready} & {io.deq.valid};
assign empty = write_pointer == read_pointer;
assign full = ((write_pointer[1:0] == read_pointer[1:0]) &
(write_pointer[2] == ~read_pointer[2]));
always @(posedge {io.CLK}) begin
if (wen) begin
assert (!full) else $error("Trying to write to full buffer");
data[write_pointer[1:0]] <= {io.enq.data};
write_pointer <= write_pointer + 1;
end
if (ren) begin
assert (!empty) else $error("Trying to read from empty buffer");
assert ({io.deq.data} == data[read_pointer[1:0]]) else
$error("Got wrong read data: io.deq.data %x != %x",
{io.deq.data}, data[read_pointer[1:0]]);
read_pointer <= read_pointer + 1;
end
end""")
class dut(m.Circuit):
name = 'test_var_timestep'
io = m.IO(x=fault.RealIn,
dt=fault.RealIn,
y=fault.RealOut,
clk=m.In(m.Clock),
rst=m.BitIn)
class DUT(m.Circuit):
io = m.IO(done=m.Out(m.Bit)) + m.ClockIO()
imm = ImmGen(32)()
ctrl = Control(32)()
counter = mantle.CounterModM(len(insts), len(insts).bit_length())
i = m.mux([iimm(i) for i in insts], counter.O)
s = m.mux([simm(i) for i in insts], counter.O)
b = m.mux([bimm(i) for i in insts], counter.O)
u = m.mux([uimm(i) for i in insts], counter.O)
j = m.mux([jimm(i) for i in insts], counter.O)
z = m.mux([zimm(i) for i in insts], counter.O)
x = m.mux([iimm(i) & -2 for i in insts], counter.O)
O = m.mux([
m.mux([
m.mux([
m.mux([
m.mux([m.mux([x, z], ctrl.imm_sel == IMM_Z), j],
ctrl.imm_sel == IMM_J), u
], ctrl.imm_sel == IMM_U), b
], ctrl.imm_sel == IMM_B), s
], ctrl.imm_sel == IMM_S), i
], ctrl.imm_sel == IMM_I)
inst = m.mux(insts, counter.O)
ctrl.inst @= inst
imm.inst @= inst
imm.sel @= ctrl.imm_sel
io.done @= counter.COUT
f.assert_immediate(imm.O == O,
failure_msg=("Counter: %d, Type: 0x%x, O: %x ?= %x",
counter.O, imm.sel, imm.O, O))
m.display("Counter: %d, Type: 0x%x, O: %x ?= %x", counter.O, imm.sel,
imm.O, O)
class _SliceWrapper(magma.Circuit):
name = name_
io = magma.IO(
I=magma.In(magma.Bits[base_width]),
O=magma.Out(magma.Bits[hi - lo]),
)
magma.wire(io.I[lo:hi], io.O)
class ALUCore(m.Circuit):
io = m.IO(a=m.In(m.UInt[16]),
b=m.In(m.UInt[16]),
opcode=m.In(m.UInt[2]),
c=m.Out(m.UInt[16]))
io.c @= m.mux([io.a + io.b, io.a - io.b, io.a * io.b, io.a / io.b],
io.opcode)
class dut(m.Circuit):
name = 'test_chan_interp'
io = m.IO(dt=fault.RealIn,
in_=fault.RealIn,
clk=m.In(m.Clock),
rst=m.BitIn,
**ios)
class dut(m.Circuit):
name = f'test_{NAME}'
io = m.IO(
a=fault.RealIn,
b=fault.RealIn,
c=m.BitOut
)
class dut(m.Circuit):
name = 'histogram_data_gen'
io = m.IO(clk=m.ClockIn,
mode=m.In(m.Bits[3]),
in0=m.In(m.Bits[n]),
in1=m.In(m.Bits[n]),
out=m.Out(m.Bits[n]))
def __init__(self, mode="pack"):
"""
Simple example that instances two stub DMA modules and is paramtrizable
over distributed versus packed register file
"""
if mode not in ["pack", "distribute"]:
raise ValueError(f"Unexpected mode {mode}")
fields = ["csr", "src_addr", "dst_addr", "txfr_len"]
data_width = 32
addr_width = math.ceil(math.log2(len(fields) * 2))
self.name = "Top_" + mode
self.io = io = m.IO(apb=APBSlave(addr_width, data_width, 0))
dmas = [DMA(name=f"dma{i}") for i in range(2)]
regs = tuple(Register(name + str(i)) for i in range(2) for name in
fields)
reg_file = RegisterFileGenerator(regs, data_width=32)(name="reg_file")
for i in range(2):
for name in fields:
m.wire(getattr(reg_file, name + str(i) + "_q"),
getattr(dmas[i], name))
m.wire(io.apb, reg_file.apb)
for i in range(2):
for name in fields:
m.wire(getattr(reg_file, name + str(i) + "_q"),
getattr(reg_file, name + str(i) + "_d"))
class _Accum(m.Circuit):
T = m.UInt[16]
io = m.IO(I=m.In(T), O=m.Out(T)) + m.ClockIO()
reg = m.Register(T)()
accum = reg.O + io.I
reg.I @= accum
io.O @= accum
class SimpleAlu(m.Circuit):
io = m.IO(a=m.In(m.UInt[4]),
b=m.In(m.UInt[4]),
opcode=m.In(m.UInt[2]),
out=m.Out(m.UInt[4]))
io.out @= m.mux([io.a + io.b, io.a - io.b, io.a, io.b], io.opcode)
class TFF(m.Circuit):
io = m.IO(O=m.Out(m.Bit), CLK=m.In(m.Clock))
reg = mantle.Register(None, name="tff_reg")
reg.CLK <= io.CLK
reg.I <= ~reg.O
io.O <= reg.O
class Foo(m.Circuit):
io = m.IO(a=m.In(m.Bits[8]),
b=m.In(m.Bits[8]),
c=m.In(m.Bits[8]),
x=m.Out(m.Bits[8]),
y=m.Out(m.Bits[8]))
io += m.ClockIO(has_resetn=True)
x = [m.bits(0, 8), m.bits(0, 8), m.bits(1, 8), m.bits(0, 8)]
if should_pass:
y = [m.bits(0, 8), m.bits(1, 8), m.bits(2, 8), m.bits(3, 8)]
else:
y = [m.bits(1, 8), m.bits(1, 8), m.bits(1, 8), m.bits(1, 8)]
count = m.Register(m.Bits[2])()
count.I @= count.O + 1
io.x @= m.mux(x, count.O)
io.y @= m.mux(y, count.O)
m.display("io.x=%x, io.y=%x", io.x, io.y).when(m.posedge(io.CLK))
if use_sva:
f.assert_(f.sva(f.not_(f.onehot(io.a)), "&&", io.b.reduce_or(),
"&&", io.x[0].value(), "|=>",
io.y.value() != f.past(io.y.value(), 2)),
name="name_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
else:
f.assert_(
# Note parens matter!
(f.not_(f.onehot(io.a)) & io.b.reduce_or() & io.x[0].value())
| f.implies | f.delay[1] | (io.y != f.past(io.y.value(), 2)),
name="name_A",
on=f.posedge(io.CLK),
disable_iff=f.not_(io.RESETN))
class SimpleALU(m.Circuit):
io = m.IO(a=m.In(m.UInt[16]),
b=m.In(m.UInt[16]),
c=m.Out(m.UInt[16]),
config_=m.In(m.Bits[2]))
io.c <= execute_alu(io.a, io.b, io.config_)
class circ(m.Circuit):
name = 's'
io = m.IO(
p=fault.ElectIn,
i=m.BitIn,
c=m.Out(m.Bits[3]),
e=fault.RealOut
)
class Main(m.Circuit):
io = m.IO(I=m.In(m.Bits[8]), x=m.In(m.Bit)) + m.ClockIO()
if use_sva:
f.assert_(f.sva(f.not_(f.onehot(io.I)), "|-> ##1", io.x),
on=f.posedge(io.CLK))
else:
f.assert_(f.not_(f.onehot(io.I)) | f.implies | f.delay[1] | io.x,
on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(a=m.In(m.Bit), b=m.In(m.Bit), c=m.In(m.Bit)) + m.ClockIO()
if sva:
seq = f.sequence(f.sva(io.b, "until_with !", io.c))
f.assert_(f.sva(f.rose(io.a), "|->", seq), on=f.posedge(io.CLK))
else:
seq = f.sequence(io.b | f.until_with | f.not_(io.c))
f.assert_(f.rose(io.a) | f.implies | seq, on=f.posedge(io.CLK))
class Main(m.Circuit):
io = m.IO(a=m.In(m.Bit), b=m.In(m.Bit), c=m.In(m.Bit)) + m.ClockIO()
if sva:
seq = f.sva(io.b, "throughout", "!", io.c, "[-> 1]")
f.assert_(f.sva(f.rose(io.a), "|->", seq), on=f.posedge(io.CLK))
else:
seq = io.b | f.throughout | f.not_(io.c | f.goto[1])
f.assert_(f.rose(io.a) | f.implies | seq, on=f.posedge(io.CLK))
class dut(m.Circuit):
name = 'clkdelay'
io = m.IO(
clk=m.In(m.Clock),
rst=m.In(m.Reset),
count=m.Out(m.Bits[n_bits]),
n_done=m.Out(m.Bit)
)
