class Main(m.Circuit):
io = m.IO(clocks=ClocksT, count=m.Out(m.UInt[3]))
count = m.Register(m.UInt[3])()
count.CLK @= io.clocks.clk0
io.count @= count(count.O + 1)
tff = m.Register(m.Bit, has_enable=True)()
tff.CLK @= io.clocks.clk0
tff.CE @= m.enable(count.O == 3)
io.clocks.clk1 @= m.clock(tff(tff.O ^ 1))
def test_reset():
assert isinstance(reset(0), ResetType)
assert isinstance(reset(1), ResetType)
assert isinstance(reset(VCC), ResetType)
assert isinstance(reset(GND), ResetType)
assert isinstance(reset(bit(0)), ResetType)
assert isinstance(reset(clock(0)), ResetType)
assert isinstance(reset(enable(0)), ResetType)
assert isinstance(reset(reset(0)), ResetType)
assert isinstance(reset(bits(0, 1)), ResetType)
assert isinstance(reset(uint(0, 1)), ResetType)
assert isinstance(reset(sint(0, 1)), ResetType)
def test_enable():
assert isinstance(enable(0), EnableType)
assert isinstance(enable(1), EnableType)
assert isinstance(enable(VCC), EnableType)
assert isinstance(enable(GND), EnableType)
assert isinstance(enable(bit(0)), EnableType)
assert isinstance(enable(clock(0)), EnableType)
assert isinstance(enable(reset(0)), EnableType)
assert isinstance(enable(enable(0)), EnableType)
assert isinstance(enable(bits(0, 1)), EnableType)
assert isinstance(enable(uint(0, 1)), EnableType)
assert isinstance(enable(sint(0, 1)), EnableType)
def test_clock():
assert isinstance(clock(0), ClockType)
assert isinstance(clock(1), ClockType)
assert isinstance(clock(VCC), ClockType)
assert isinstance(clock(GND), ClockType)
assert isinstance(clock(bit(0)), ClockType)
assert isinstance(clock(clock(0)), ClockType)
assert isinstance(clock(reset(0)), ClockType)
assert isinstance(clock(enable(0)), ClockType)
assert isinstance(clock(bits(0, 1)), ClockType)
assert isinstance(clock(uint(0, 1)), ClockType)
assert isinstance(clock(sint(0, 1)), ClockType)
from magma import wire, clock, bit, compile, EndCircuit
from loam.boards.icestick import IceStick, Register
icestick = IceStick()
icestick.Clock.on()
for i in range(4):
icestick.J1[i].input().on()
icestick.J3[i].output().on()
icestick.J1[4].input().on()
main = icestick.main()
reg = Register(4)
wire(clock(bit(main.CLK) & main.J1[4]), reg.CLK)
wire(reg(main.J1[0:4]), main.J3)
EndCircuit()