def definition(io):
adder_cycle = mantle.Add(n, cin=False, cout=False)
reg_cycle = mantle.Register(n, has_reset=True)
adder_idx = mantle.Add(b, cin=False, cout=False)
reg_idx = mantle.Register(b, has_ce=True)
wire(io.CLK, reg_cycle.CLK)
wire(io.CLK, reg_idx.CLK)
wire(reg_cycle.O, adder_cycle.I0)
wire(bits(1, n), adder_cycle.I1)
wire(adder_cycle.O, reg_cycle.I)
comparison_cycle = mantle.EQ(n)
wire(reg_cycle.O, comparison_cycle.I0)
wire(bits(num_cycles - 1, n), comparison_cycle.I1)
# if cycle-th is the last, then switch to next idx (accumulate idx) and clear cycle
wire(comparison_cycle.O, reg_cycle.RESET)
wire(comparison_cycle.O, reg_idx.CE)
comparison_idx = mantle.EQ(b)
wire(reg_idx.O, comparison_idx.I0)
wire(bits(num_classes - 1, b), comparison_idx.I1)
wire(reg_idx.O, adder_idx.I0)
wire(bits(0, b - 1), adder_idx.I1[1:])
nand_gate = mantle.NAnd()
wire(comparison_cycle.O, nand_gate.I0)
wire(comparison_idx.O, nand_gate.I1)
# after all idx rows, we stop accumulating idx
wire(nand_gate.O, adder_idx.I1[0])
wire(adder_idx.O, reg_idx.I)
wire(reg_idx.O, io.IDX)
wire(adder_cycle.O, io.CYCLE)
def create_io1out_pad():
cb = m.DefineCircuit("io1out_pad", "clk", m.In(m.Clock), "rst",
m.In(m.Reset), "config_data", m.In(m.Bits(32)),
"config_addr", m.In(m.Bits(32)), "tile_id",
m.In(m.Bits(16)), "pin_0", m.In(m.Bit), "pin_1",
m.In(m.Bit), "pin_2", m.In(m.Bit), "pin_3",
m.In(m.Bit), "top_pin", m.Out(m.Bits(1)))
# Configuration data
config_reg = mantle.Register(32, init=0, has_ce=True, has_reset=True)
addr_match = mantle.EQ(16)
m.wire(addr_match.I0, cb.config_addr[0:16])
m.wire(addr_match.I1, cb.tile_id)
m.wire(addr_match.O, config_reg.CE)
m.wire(cb.config_data, config_reg.I)
m.wire(cb.clk, config_reg.CLK)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], cb.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Config mux
config_mux = mantle.Mux(height=4, width=1)
m.wire(config_mux.O, cb.top_pin)
m.wire(config_mux.S, config_reg.O[0:2])
m.wire(cb.pin_0, config_mux.I0[0])
m.wire(cb.pin_1, config_mux.I1[0])
m.wire(cb.pin_2, config_mux.I2[0])
m.wire(cb.pin_3, config_mux.I3[0])
m.EndDefine()
return cb
def definition(io):
# IF - get cycle_id, label_index_id
controller = Controller()
reg_1_cycle = mantle.Register(n)
reg_1_control = mantle.DFF(init=1)
wire(io.CLK, controller.CLK)
wire(io.CLK, reg_1_cycle.CLK)
wire(io.CLK, reg_1_control.CLK)
reg_1_idx = controller.IDX
wire(controller.CYCLE, reg_1_cycle.I)
wire(1, reg_1_control.I)
# RR - get weight block, image block of N bits
readROM = ReadROM()
wire(reg_1_idx, readROM.IDX)
wire(reg_1_cycle.O, readROM.CYCLE)
reg_2 = mantle.Register(N + b + n)
reg_2_control = mantle.DFF()
reg_2_weight = readROM.WEIGHT
wire(io.CLK, reg_2.CLK)
wire(io.CLK, readROM.CLK)
wire(io.CLK, reg_2_control.CLK)
wire(readROM.IMAGE, reg_2.I[:N])
wire(reg_1_idx, reg_2.I[N:N + b])
wire(reg_1_cycle.O, reg_2.I[N + b:])
wire(reg_1_control.O, reg_2_control.I)
# EX - NXOr for multiplication, pop count and accumulate the result for activation
multiplier = mantle.NXOr(height=2, width=N)
bit_counter = DefineBitCounter(N)()
adder = mantle.Add(n_bc_adder, cin=False, cout=False)
mux_for_adder_0 = mantle.Mux(height=2, width=n_bc_adder)
mux_for_adder_1 = mantle.Mux(height=2, width=n_bc_adder)
reg_3_1 = mantle.Register(n_bc_adder)
reg_3_2 = mantle.Register(b + n)
wire(io.CLK, reg_3_1.CLK)
wire(io.CLK, reg_3_2.CLK)
wire(reg_2_weight, multiplier.I0)
wire(reg_2.O[:N], multiplier.I1)
wire(multiplier.O, bit_counter.I)
wire(bits(0, n_bc_adder), mux_for_adder_0.I0)
wire(bit_counter.O, mux_for_adder_0.I1[:n_bc])
if n_bc_adder > n_bc:
wire(bits(0, n_bc_adder - n_bc), mux_for_adder_0.I1[n_bc:])
# only when data read is ready (i.e. control signal is high), accumulate the pop count result
wire(reg_2_control.O, mux_for_adder_0.S)
wire(reg_3_1.O, mux_for_adder_1.I0)
wire(bits(0, n_bc_adder), mux_for_adder_1.I1)
if n == 4:
comparison_3 = SB_LUT4(LUT_INIT=int('0' * 15 + '1', 2))
wire(
reg_2.O[N + b:],
bits([
comparison_3.I0, comparison_3.I1, comparison_3.I2,
comparison_3.I3
]))
else:
comparison_3 = mantle.EQ(n)
wire(reg_2.O[N + b:], comparison_3.I0)
wire(bits(0, n), comparison_3.I1)
wire(comparison_3.O, mux_for_adder_1.S)
wire(mux_for_adder_0.O, adder.I0)
wire(mux_for_adder_1.O, adder.I1)
wire(adder.O, reg_3_1.I)
wire(reg_2.O[N:], reg_3_2.I)
# CF - classify the image
classifier = Classifier()
reg_4 = mantle.Register(n + b)
reg_4_idx = classifier.O
wire(io.CLK, classifier.CLK)
wire(io.CLK, reg_4.CLK)
wire(reg_3_1.O, classifier.I)
wire(reg_3_2.O[:b], classifier.IDX)
wire(reg_3_2.O, reg_4.I)
# WB - wait to show the result until the end
reg_5 = mantle.Register(b, has_ce=True)
comparison_5_1 = mantle.EQ(b)
comparison_5_2 = mantle.EQ(n)
and_gate = mantle.And()
wire(io.CLK, reg_5.CLK)
wire(reg_4_idx, reg_5.I)
wire(reg_4.O[:b], comparison_5_1.I0)
wire(bits(num_classes - 1, b), comparison_5_1.I1)
wire(reg_4.O[b:], comparison_5_2.I0)
wire(bits(num_cycles - 1, n), comparison_5_2.I1)
wire(comparison_5_1.O, and_gate.I0)
wire(comparison_5_2.O, and_gate.I1)
wire(and_gate.O, reg_5.CE)
wire(reg_5.O, io.O)
# latch the light indicating the end
reg_6 = mantle.DFF()
wire(io.CLK, reg_6.CLK)
or_gate = mantle.Or()
wire(and_gate.O, or_gate.I0)
wire(reg_6.O, or_gate.I1)
wire(or_gate.O, reg_6.I)
wire(reg_6.O, io.D)
def definition(io):
load = io.LOAD
baud = rising(io.SCK) | falling(io.SCK)
valid_counter = mantle.CounterModM(buf_size, 12, has_ce=True)
m.wire(load & baud, valid_counter.CE)
valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)] # len = 32
valid = m.GND
for i in valid_list:
valid = valid | mantle.Decode(i, 12)(valid_counter.O)
# register on input
st_in = mantle.Register(width, has_ce=True)
st_in(io.DATA)
m.wire(load, st_in.CE)
# --------------------------DOWNSCALING----------------------------- #
# downscale the image from 352x288 to 32x32
Downscale = m.DeclareCircuit(
'Downscale',
"I_0_0", m.In(m.Array(1, m.Array(1, m.Array(width, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock),
"O", m.Out(m.Array(width, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(width) # needed for Add16 definition
# --------------------------FILL IMG RAM--------------------------- #
# each valid output of dscale represents an entry of 32x32 binary image
# accumulate each group of 32 entries into a 32-bit value representing a row
col = mantle.CounterModM(32, 6, has_ce=True)
col_ce = rising(valid)
m.wire(col_ce, col.CE)
# shift each bit in one at a time until we get an entire row
px_bit = mantle.ULE(16)(dscale.O, m.uint(THRESH, 16)) & valid
row_reg = mantle.SIPO(32, has_ce=True)
row_reg(px_bit)
m.wire(col_ce, row_reg.CE)
# reverse the row bits since the image is flipped
row = reverse(row_reg.O)
rowaddr = mantle.Counter(6, has_ce=True)
img_full = mantle.SRFF(has_ce=True)
img_full(mantle.EQ(6)(rowaddr.O, m.bits(32, 6)), 0)
m.wire(falling(col.COUT), img_full.CE)
row_ce = rising(col.COUT) & ~img_full.O
m.wire(row_ce, rowaddr.CE)
waddr = rowaddr.O[:5]
rdy = col.COUT & ~img_full.O
pulse_count = mantle.Counter(2, has_ce=True)
we = mantle.UGE(2)(pulse_count.O, m.uint(1, 2))
pulse_count(CE=(we|rdy))
# ---------------------------UART OUTPUT----------------------------- #
row_load = row_ce
row_baud = mantle.FF()(baud)
uart_row = UART(32)
uart_row(CLK=io.CLK, BAUD=row_baud, DATA=row, LOAD=row_load)
uart_addr = UART(5)
uart_addr(CLK=io.CLK, BAUD=row_baud, DATA=waddr, LOAD=row_load)
m.wire(waddr, io.WADDR)
m.wire(img_full, io.DONE) #img_full
m.wire(uart_row, io.UART) #uart_st
m.wire(row, io.O)
m.wire(we, io.VALID)
m.wire(valid, io.T0)
m.wire(uart_addr, io.T1)
def definition(cam):
edge_f = falling(cam.SCK)
edge_r = rising(cam.SCK)
# ROM to store commands
rom_index = mantle.Counter(4, has_ce=True)
rom = ROM16(4, init, rom_index.O)
# Message length is 16 bits, setup counter to generate done signal
# after EOM
done_counter = mantle.Counter(5, has_ce=True, has_reset=True)
count = done_counter.O
done = mantle.Decode(16, 5)(count)
# State machine to generate run signal (enable)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0])
run_n(done, trigger, run)
run(run_n)
m.wire(edge_f, run.CE)
# Reset the message length counter after done
run_reset = mantle.LUT2(I0 | ~I1)(done, run)
done_counter(CE=edge_r, RESET=run_reset)
# State variables for high-level state machine
ready = mantle.LUT2(~I0 & I1)(run, edge_f)
start = mantle.ULE(4)(rom_index.O, m.uint(3, 4))
burst = mantle.UGE(4)(rom_index.O, m.uint(9, 4))
# Shift register to store 16-bit command|data to send
mosi = mantle.PISO(16, has_ce=True)
# SPI enable is negative of load-don't load and shift out data at the
# same time
enable = mantle.LUT3(I0 & ~I1 & ~I2)(trigger, run, burst)
mosi(~burst, rom.O, enable)
m.wire(edge_f, mosi.CE)
# Shit register to read in 8-bit data
miso = mantle.SIPO(8, has_ce=True)
miso(cam.MISO)
valid = mantle.LUT2(~I0 & I1)(enable, edge_r)
m.wire(valid, miso.CE)
# Capture done state variable
cap_done = mantle.SRFF(has_ce=True)
cap_done(mantle.EQ(8)(miso.O, m.bits(0x08, 8)), 0)
m.wire(enable & edge_r, cap_done.CE)
# Use state variables to determine what commands are sent (how)
increment = mantle.LUT4(I0 & (I1 | I2) & ~I3)(
ready, start, cap_done, burst)
m.wire(increment, rom_index.CE)
# wire outputs
m.wire(enable, cam.EN)
m.wire(mosi.O, cam.MOSI)
m.wire(miso.O, cam.DATA)
m.wire(burst, cam.VALID)
# --------------------------UART OUTPUT---------------------------- #
# run UART at 2x SPI rate to allow it to keep up
baud = edge_r | edge_f
# reset when SPI burst read (image transfer) begins
ff = mantle.FF(has_ce=True)
m.wire(edge_r, ff.CE)
u_reset = mantle.LUT2(I0 & ~I1)(burst, ff(burst))
# UART data out every 8 bits
u_counter = mantle.CounterModM(8, 3, has_ce=True, has_reset=True)
u_counter(CE=edge_r, RESET=u_reset)
load = burst & rising(u_counter.COUT)
uart = UART(8)
uart(CLK=cam.CLK, BAUD=baud, DATA=miso, LOAD=load)
# wire output
m.wire(uart, cam.UART)
# generate signal for when transfer is done
data_count = mantle.Counter(18, has_ce=True)
tx_done = mantle.SRFF(has_ce=True)
# transfer has size 153600 bytes, first 2 bytes are ignored
tx_done(mantle.EQ(18)(data_count.O, m.bits(153602, 18)), 0)
m.wire(load, tx_done.CE)
m.wire(load, data_count.CE)
# wire output
m.wire(tx_done, cam.DONE)
def create_pe_tile():
pe = m.DefineCircuit(
"pe_tile", "clk", m.In(m.Clock), "rst", m.In(m.Reset), "config_data",
m.In(m.Bits(32)), "config_addr", m.In(m.Bits(32)), "tile_id",
m.In(m.Bits(16)), "side_0_track_0_in", m.In(m.Bits(1)),
"side_0_track_1_in", m.In(m.Bits(1)), "side_0_track_2_in",
m.In(m.Bits(1)), "side_0_track_3_in", m.In(m.Bits(1)),
"side_1_track_0_in", m.In(m.Bits(1)), "side_1_track_1_in",
m.In(m.Bits(1)), "side_1_track_2_in", m.In(m.Bits(1)),
"side_1_track_3_in", m.In(m.Bits(1)), "side_2_track_0_in",
m.In(m.Bits(1)), "side_2_track_1_in", m.In(m.Bits(1)),
"side_2_track_2_in", m.In(m.Bits(1)), "side_2_track_3_in",
m.In(m.Bits(1)), "side_3_track_0_in", m.In(m.Bits(1)),
"side_3_track_1_in", m.In(m.Bits(1)), "side_3_track_2_in",
m.In(m.Bits(1)), "side_3_track_3_in", m.In(m.Bits(1)),
"side_0_track_0_out", m.Out(m.Bits(1)), "side_0_track_1_out",
m.Out(m.Bits(1)), "side_0_track_2_out", m.Out(m.Bits(1)),
"side_0_track_3_out", m.Out(m.Bits(1)), "side_1_track_0_out",
m.Out(m.Bits(1)), "side_1_track_1_out", m.Out(m.Bits(1)),
"side_1_track_2_out", m.Out(m.Bits(1)), "side_1_track_3_out",
m.Out(m.Bits(1)), "side_2_track_0_out", m.Out(m.Bits(1)),
"side_2_track_1_out", m.Out(m.Bits(1)), "side_2_track_2_out",
m.Out(m.Bits(1)), "side_2_track_3_out", m.Out(m.Bits(1)),
"side_3_track_0_out", m.Out(m.Bits(1)), "side_3_track_1_out",
m.Out(m.Bits(1)), "side_3_track_2_out", m.Out(
m.Bits(1)), "side_3_track_3_out", m.Out(m.Bits(1)))
# Configuration data
config_reg = mantle.Register(32, init=0, has_ce=True, has_reset=True)
addr_match = mantle.EQ(16)
m.wire(addr_match.I0, pe.config_addr[0:16])
m.wire(addr_match.I1, pe.tile_id)
m.wire(addr_match.O, config_reg.CE)
m.wire(pe.config_data, config_reg.I)
m.wire(pe.clk, config_reg.CLK)
rst_inv = mantle.Invert(1)
m.wire(rst_inv.I[0], pe.rst)
m.wire(rst_inv.O[0], config_reg.RESET)
# Configure sb = 6, cb0 = 4, cb1 = 5, clb = 7
config_cb0_eq = mantle.EQ(16)
m.wire(m.uint(4, 16), config_cb0_eq.I0)
m.wire(pe.config_addr[16:32], config_cb0_eq.I1)
config_cb1_eq = mantle.EQ(16)
m.wire(m.uint(5, 16), config_cb1_eq.I0)
m.wire(pe.config_addr[16:32], config_cb1_eq.I1)
config_clb_eq = mantle.EQ(16)
m.wire(m.uint(7, 16), config_clb_eq.I0)
m.wire(pe.config_addr[16:32], config_clb_eq.I1)
config_sb_eq = mantle.EQ(16)
m.wire(m.uint(6, 16), config_sb_eq.I0)
m.wire(pe.config_addr[16:32], config_sb_eq.I1)
config_cb0 = mantle.And(2, 1)
m.wire(config_cb0.I0[0], config_cb0_eq.O)
m.wire(config_cb0.I1[0], addr_match.O)
config_cb1 = mantle.And(2, 1)
m.wire(config_cb1.I0[0], config_cb1_eq.O)
m.wire(config_cb1.I1[0], addr_match.O)
config_clb = mantle.And(2, 1)
m.wire(config_clb.I0[0], config_clb_eq.O)
m.wire(config_clb.I1[0], addr_match.O)
config_sb = mantle.And(2, 1)
m.wire(config_sb.I0[0], config_sb_eq.O)
m.wire(config_sb.I1[0], addr_match.O)
# Add ands!
# # CB0
cb0 = create_connect_box(1)()
m.wire(pe.clk, cb0.clk)
m.wire(pe.rst, cb0.rst)
m.wire(pe.config_data, cb0.config_data)
m.wire(config_cb0.O[0], cb0.config_en)
# CB1
cb1 = create_connect_box(1)()
m.wire(pe.clk, cb1.clk)
m.wire(pe.rst, cb1.rst)
m.wire(pe.config_data, cb1.config_data)
m.wire(config_cb1.O[0], cb1.config_en)
# CLB
clb = create_clb(1)()
m.wire(pe.clk, clb.clk)
m.wire(pe.rst, clb.rst)
m.wire(pe.config_data, clb.config_data)
m.wire(config_clb.O[0], clb.config_en)
# Switch box
sb = create_switch_box(1)()
m.wire(pe.clk, sb.clk)
m.wire(pe.rst, sb.rst)
m.wire(pe.config_data, sb.config_data)
m.wire(config_sb.O[0], sb.config_en)
m.wire(clb.result, sb.clb_result)
for side in range(0, 4):
for track in range(0, 4):
m.wire(
getattr(pe,
'side_' + str(side) + '_track_' + str(track) + '_in'),
getattr(sb,
'side_' + str(side) + '_track_' + str(track) + '_in'))
for side in range(0, 4):
for track in range(0, 4):
m.wire(
getattr(pe,
'side_' + str(side) + '_track_' + str(track) + '_out'),
getattr(sb,
'side_' + str(side) + '_track_' + str(track) + '_out'))
# Wiring up CLB, SB and CBs
m.wire(pe.side_0_track_0_in, cb0.track_0_in)
m.wire(pe.side_0_track_1_in, cb0.track_1_in)
m.wire(pe.side_0_track_2_in, cb0.track_2_in)
m.wire(pe.side_0_track_3_in, cb0.track_3_in)
m.wire(sb.side_0_track_0_out, cb0.track_0_out)
m.wire(sb.side_0_track_1_out, cb0.track_1_out)
m.wire(sb.side_0_track_2_out, cb0.track_2_out)
m.wire(sb.side_0_track_3_out, cb0.track_3_out)
m.wire(cb0.out, clb.operand0)
m.wire(pe.side_1_track_0_in, cb1.track_0_in)
m.wire(pe.side_1_track_1_in, cb1.track_1_in)
m.wire(pe.side_1_track_2_in, cb1.track_2_in)
m.wire(pe.side_1_track_3_in, cb1.track_3_in)
m.wire(sb.side_1_track_0_out, cb1.track_0_out)
m.wire(sb.side_1_track_1_out, cb1.track_1_out)
m.wire(sb.side_1_track_2_out, cb1.track_2_out)
m.wire(sb.side_1_track_3_out, cb1.track_3_out)
m.wire(cb1.out, clb.operand1)
m.EndDefine()
return pe
def equals_cmp(a, b, width):
eqC = mantle.EQ(width)
m.wire(eqC.I0, a)
m.wire(eqC.I1, b)
return eqC
def definition(io):
feedthrough_count = num_tracks
for i in range(0, len(feedthrough_outputs)):
feedthrough_count -= feedthrough_outputs[i] == '1'
mux_sel_bit_count = int(
math.ceil(
math.log(num_tracks - feedthrough_count + has_constant,
2)))
constant_bit_count = has_constant * width
config_bit_count = mux_sel_bit_count + constant_bit_count
config_reg_width = int(math.ceil(config_bit_count / 32.0) * 32)
reset_val = num_tracks - feedthrough_count + has_constant - 1
config_reg_reset_bit_vector = []
CONFIG_DATA_WIDTH = 32
if (constant_bit_count > 0):
print('constant_bit_count =', constant_bit_count)
reset_bits = m.bitutils.int2seq(default_value,
constant_bit_count)
default_bits = m.bitutils.int2seq(reset_val, mux_sel_bit_count)
print('default val bits =', reset_bits)
print('reset val bits =', default_bits)
# concat before assert
config_reg_reset_bit_vector += default_bits
config_reg_reset_bit_vector += reset_bits
config_reg_reset_bit_vector = \
m.bitutils.seq2int(config_reg_reset_bit_vector)
print('reset bit vec as int =', config_reg_reset_bit_vector)
else:
config_reg_reset_bit_vector = reset_val
config_cb = mantle.Register(config_reg_width,
init=config_reg_reset_bit_vector,
has_ce=True,
has_reset=True)
config_addr_zero = mantle.EQ(8)
m.wire(m.uint(0, 8), config_addr_zero.I0)
m.wire(config_addr_zero.I1, io.config_addr[24:32])
config_en_set = mantle.And(2, 1)
m.wire(config_en_set.I0, m.uint(1, 1))
m.wire(config_en_set.I1[0], io.config_en)
config_en_set_and_addr_zero = mantle.And(2, 1)
m.wire(config_en_set_and_addr_zero.I0, config_en_set.O)
m.wire(config_en_set_and_addr_zero.I1[0], config_addr_zero.O)
m.wire(config_en_set_and_addr_zero.O[0], config_cb.CE)
config_set_mux = mantle.Mux(height=2, width=CONFIG_DATA_WIDTH)
m.wire(config_set_mux.I0, config_cb.O)
m.wire(config_set_mux.I1, io.config_addr)
m.wire(config_set_mux.S, config_en_set_and_addr_zero.O[0])
m.wire(config_cb.RESET, io.reset)
m.wire(config_cb.I, io.config_data)
# Setting read data
read_data_mux = mantle.Mux(height=2, width=CONFIG_DATA_WIDTH)
m.wire(read_data_mux.S,
equals_cmp(io.config_addr[24:32], m.uint(0, 8), 8).O)
m.wire(read_data_mux.I1, config_cb.O)
m.wire(read_data_mux.I0, m.uint(0, 32))
m.wire(io.read_data, read_data_mux.O)
pow_2_tracks = power_log(num_tracks)
print('# of tracks =', pow_2_tracks)
output_mux = mantle.Mux(height=pow_2_tracks, width=width)
m.wire(output_mux.S, config_cb.O[0:math.ceil(math.log(width, 2))])
# Note: Uncomment this line for select to make the unit test fail!
# m.wire(output_mux.S, m.uint(0, math.ceil(math.log(width, 2))))
# This is only here because this is the way the switch box numbers
# things.
# We really should get rid of this feedthrough parameter
sel_out = 0
for i in range(0, pow_2_tracks):
# in_track = 'I' + str(i)
if (i < num_tracks):
if (feedthrough_outputs[i] == '1'):
m.wire(getattr(output_mux, 'I' + str(sel_out)),
getattr(io, 'in_' + str(i)))
sel_out += 1
if (has_constant == 0):
while (sel_out < pow_2_tracks):
m.wire(getattr(output_mux, 'I' + str(sel_out)),
m.uint(0, width))
sel_out += 1
else:
const_val = config_cb.O[mux_sel_bit_count:mux_sel_bit_count +
constant_bit_count]
while (sel_out < pow_2_tracks):
m.wire(getattr(output_mux, 'I' + str(sel_out)), const_val)
sel_out += 1
# NOTE: This is a dummy! fix it later!
m.wire(output_mux.O, io.out)
return
def definition(io):
load = io.LOAD
baud = io.BAUD
valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True)
m.wire(load & baud, valid_counter.CE)
valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)]
valid = m.GND
for i in valid_list:
valid = valid | mantle.Decode(i, 13)(valid_counter.O)
# register on input
st_in = mantle.Register(16, has_ce=True)
st_in(io.DATA)
m.wire(load, st_in.CE)
# --------------------------DOWNSCALING----------------------------- #
# downscale the image from 320x240 to 16x16
Downscale = m.DeclareCircuit(
'Downscale',
"I_0_0", m.In(m.Array(1, m.Array(1, m.Array(16, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock),
"O", m.Out(m.Array(16, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(16) # needed for Add16 definition
# --------------------------FILL IMG RAM--------------------------- #
# each valid output of dscale represents an entry of 16x16 binary image
# accumulate each group of 16 entries into a 16-bit value representing
# a row of the image
col = mantle.Counter(4, has_ce=True)
row_full = mantle.SRFF(has_ce=True)
row_full(mantle.EQ(4)(col.O, m.bits(15, 4)), 0)
m.wire(falling(dscale.V), row_full.CE)
col_ce = rising(dscale.V) & ~row_full.O
m.wire(col_ce, col.CE)
row = mantle.Counter(4, has_ce=True)
img_full = mantle.SRFF(has_ce=True)
img_full(mantle.EQ(4)(row.O, m.bits(15, 4)), 0)
m.wire(falling(col.COUT), img_full.CE)
row_ce = rising(col.COUT) & ~img_full.O
m.wire(row_ce, row.CE)
# ---------------------------UART OUTPUT----------------------------- #
uart_st = UART(16)
uart_st(CLK=io.CLK, BAUD=baud, DATA=dscale.O, LOAD=load)
m.wire(row.O, io.ROW)
m.wire(img_full.O, io.DONE)
m.wire(uart_st.O, io.UART)
def definition(io):
comp = mantle.EQ(8)
magma.wire(magma.uint(ord(c[0]), 8), comp.I0)
magma.wire(io.char, comp.I1)
magma.wire(comp.O, io.match)
def definition(io):
load = io.LOAD
baud = rising(io.SCK) | falling(io.SCK)
valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True)
m.wire(load & baud, valid_counter.CE)
valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)]
valid = m.GND
for i in valid_list:
valid = valid | mantle.Decode(i, 13)(valid_counter.O)
# register on input
st_in = mantle.Register(16, has_ce=True)
st_in(io.DATA)
m.wire(load, st_in.CE)
# --------------------------DOWNSCALING----------------------------- #
# downscale the image from 320x240 to 16x16
Downscale = m.DeclareCircuit(
'Downscale',
"I_0_0", m.In(m.Array(1, m.Array(1, m.Array(16, m.Bit)))),
"WE", m.In(m.Bit), "CLK", m.In(m.Clock),
"O", m.Out(m.Array(16, m.Bit)), "V", m.Out(m.Bit))
dscale = Downscale()
m.wire(st_in.O, dscale.I_0_0[0][0])
m.wire(1, dscale.WE)
m.wire(load, dscale.CLK)
add16 = mantle.Add(16) # needed for Add16 definition
# --------------------------FILL IMG RAM--------------------------- #
# each valid output of dscale represents a pixel in 16x16 binary image
# accumulate each group of 16 pixels into a 16-bit value representing
# a row in the image
col = mantle.CounterModM(16, 5, has_ce=True)
col_ce = rising(valid)
m.wire(col_ce, col.CE)
# shift each bit in one at a time until we get an entire row
px_bit = mantle.ULE(16)(dscale.O, m.uint(THRESH, 16)) & valid
row_reg = mantle.SIPO(16, has_ce=True)
row_reg(px_bit)
m.wire(col_ce, row_reg.CE)
# reverse the row bits since the image is flipped
row = reverse(row_reg.O)
rowaddr = mantle.Counter(5, has_ce=True)
img_full = mantle.SRFF(has_ce=True)
img_full(mantle.EQ(5)(rowaddr.O, m.bits(16, 5)), 0)
m.wire(falling(col.COUT), img_full.CE)
row_ce = rising(col.COUT) & ~img_full.O
m.wire(row_ce, rowaddr.CE)
waddr = rowaddr.O[:4]
# we_counter = mantle.CounterModM(16, 5, has_ce=True)
# m.wire(rising(valid), we_counter.CE)
rdy = col.COUT & ~img_full.O
pulse_count = mantle.Counter(5, has_ce=True)
we = mantle.UGE(5)(pulse_count.O, m.uint(1, 5))
pulse_count(CE=(we | rdy))
# ---------------------------UART OUTPUT----------------------------- #
row_load = row_ce
row_baud = mantle.FF()(baud)
uart_row = UART(16)
uart_row(CLK=io.CLK, BAUD=row_baud, DATA=row, LOAD=row_load)
uart_addr = UART(4)
uart_addr(CLK=io.CLK, BAUD=row_baud, DATA=waddr, LOAD=row_load)
# split 16-bit row data into 8-bit packets so it can be parsed
low_byte = row & LOW_MASK
high_byte = row & HIGH_MASK
uart_counter = mantle.CounterModM(8, 4, has_ce=True)
m.wire(rising(valid), uart_counter.CE)
m.wire(waddr, io.WADDR)
m.wire(img_full, io.DONE)
m.wire(uart_row, io.UART)
m.wire(row, io.O)
m.wire(we, io.VALID)
# decrease the frequency to avoid timing violation counter = mantle.Counter(5) sclk = counter.O[4] baud = mantle.FF()(rising(sclk) | falling(sclk)) rom_idx = mantle.Counter(5, has_ce=True) addr = rom_idx.O[:4] bit_counter = mantle.Counter(5, has_ce=True) m.wire(rising(sclk), bit_counter.CE) we = mantle.Decode(0, 5)(bit_counter.O) load = rising(we) full = mantle.SRFF(has_ce=True) check = mantle.EQ(5)(rom_idx.O, m.bits(16, 5)) full(check, 0) m.wire(falling(sclk), full.CE) rom_ce = load & ~full.O m.wire(rom_ce, rom_idx.CE) rom = ROM16(4, num_data, addr) uart = UART(4) uart(CLK=main.CLKIN, BAUD=baud, DATA=addr, LOAD=load) pipeline = Pipeline() m.wire(sclk, pipeline.CLK) m.wire(rom.O, pipeline.DATA) m.wire(addr, pipeline.WADDR)
img_list = [
0, 0, 0, 0, 960, 2016, 1632, 1632, 2016, 960, 224, 224, 224, 224, 64, 0
] # 9, first row->last row
# img_list = [0, 0, 0, 896, 984, 3680, 7216, 6204, 14456, 14448, 8160, 3840,
# 0, 0, 0, 0] # 0
# img_list = range(2, 18)
num_data = [m.uint(img_list[i], 16) for i in range(16)]
# decrease the frequency to avoid timing violation
counter = mantle.Counter(4)
sclk = counter.O[-1]
rom_idx = mantle.Counter(4, has_ce=True)
full = mantle.SRFF(has_ce=True)
check = mantle.EQ(4)(rom_idx.O, m.bits(15, 4))
full(check, 0)
m.wire(falling(sclk), full.CE)
rom_ce = rising(sclk) & ~full.O
m.wire(rom_ce, rom_idx.CE)
rom = ROM16(4, num_data, rom_idx.O)
pipeline = Pipeline()
m.wire(sclk, pipeline.CLK)
m.wire(rom.O, pipeline.DATA)
m.wire(rom_idx.O, pipeline.WADDR)
m.wire(~full.O, pipeline.WE)
m.wire(full.O, pipeline.RUN)
m.wire(pipeline.O[:4], m.bits([main.D1, main.D2, main.D3, main.D4]))
