def test_generate(self): xor = XOR(self.bank, self.main, 16) gen = vhdl.VHDLGenerator(self.machine) ml = MemoryList(self.main) ml.add_memory(Subsystem(0, 8, 0, xor)) result = gen.generate(ml) self.assertNotEqual(result, None) self.assertEqual(self.main.generated, 1) self.assertEqual(self.bank.generated, 1)
def test_generate(self): s = SPM(self.main, word_size=8, size=1024, access_time=1, cycle_time=1) gen = vhdl.VHDLGenerator(self.machine) ml = MemoryList(self.main) ml.add_memory(Subsystem(0, 8, 0, s)) result = gen.generate(ml) self.assertNotEqual(result, None) self.assertEqual(self.main.generated, 1)
def test_generate(self): split = Split(self.bank0, self.bank1, self.main, offset=128) gen = vhdl.VHDLGenerator(self.machine) ml = MemoryList(self.main) ml.add_memory(Subsystem(0, 8, 0, split)) result = gen.generate(ml) self.assertNotEqual(result, None) self.assertEqual(self.main.generated, 1) self.assertEqual(self.bank0.generated, 1) self.assertEqual(self.bank1.generated, 1)
def test_generate(self): cache = Cache(self.main, line_count=4, line_size=2, associativity=2, policy=CachePolicy.LRU, access_time=1, cycle_time=1, write_back=True) gen = vhdl.VHDLGenerator(self.machine) ml = MemoryList(self.main) ml.add_memory(Subsystem(0, 2, 0, cache)) result = gen.generate(ml) self.assertNotEqual(result, None) self.assertEqual(self.main.generated, 1)