def insert_recorder(mhs, index, comment, inst_name_log, ver, axi_file, width, net, clock):
"""
Inserts an nf10_axis_sim core with provided arguments.
"""
if width is None:
width = ""
else:
width = "PARAMETER C_S_AXIS_DATA_WIDTH = %s\n" % width
mhs[index:index] = mhstools.parse_mhs(
cStringIO.StringIO(
"""\
#
# %s
BEGIN nf10_axis_sim_record
PARAMETER INSTANCE = %s
PARAMETER HW_VER = %s
PARAMETER output_file = %s
%s\
BUS_INTERFACE S_AXIS = %s
PORT aclk = %s
PORT counter = %s_counter
PORT activity_rec = %s_activity_rec
END
"""
% (comment, inst_name_log, ver, axi_file, width, net, clock, inst_name_log, inst_name_log)
)
)
def insert_stimulator( mhs, index, comment, inst_name, ver, axi_file, width, net, clock, reset, inst_name_log ):
"""
Inserts an nf10_axis_sim core with provided arguments.
"""
if width is None:
width = ''
else:
width = 'PARAMETER C_M_AXIS_DATA_WIDTH = %s\n' % width
mhs[index:index] = mhstools.parse_mhs( cStringIO.StringIO( """\
#
# %s
BEGIN nf10_axis_sim_stim
PARAMETER INSTANCE = %s
PARAMETER HW_VER = %s
PARAMETER input_file = %s
%s\
BUS_INTERFACE M_AXIS = %s
PORT aclk = %s
PORT aresetn = %s
PORT counter = %s_counter
PORT activity_stim = %s_activity_stim
PORT barrier_req = %s_barrier_req
PORT barrier_proceed = nf10_barrier_0_barrier_proceed
END
""" % (comment, inst_name, ver, axi_file, width, net, clock, reset, inst_name_log, inst_name, inst_name) ) )
def insert_barrier(mhs, index):
mhs[index:index] = mhstools.parse_mhs(cStringIO.StringIO(
"""\
# BARRIER
BEGIN nf10_barrier
PARAMETER INSTANCE = nf10_barrier_0
PARAMETER HW_VER = 1.00.a
PORT activity_stim = %s
PORT activity_rec = %s
PORT activity_trans_sim = nf10_axi_sim_transactor_0_activity_trans_sim
PORT activity_trans_log = nf10_axi_sim_transactor_0_activity_trans_log
PORT barrier_req = %s
PORT barrier_req_trans = nf10_axi_sim_transactor_0_barrier_req_trans
PORT barrier_proceed = nf10_barrier_0_barrier_proceed
END
# TRANSACTOR
BEGIN nf10_axi_sim_transactor
PARAMETER INSTANCE = nf10_axi_sim_transactor_0
PARAMETER HW_VER = 1.10.a
BUS_INTERFACE M_AXI = axi_interconnect_0
PORT M_AXI_ARESETN = proc_sys_reset_0_Peripheral_aresetn
PORT M_AXI_ACLK = clk_100_0000MHz
PORT activity_trans_sim = nf10_axi_sim_transactor_0_activity_trans_sim
PORT activity_trans_log = nf10_axi_sim_transactor_0_activity_trans_log
PORT barrier_req_trans = nf10_axi_sim_transactor_0_barrier_req_trans
PORT barrier_proceed = nf10_barrier_0_barrier_proceed
END
""" %(result_1, result, result_2)))
def insert_stimulator( mhs, index, comment, inst_name, ver, axi_file, width, net, clock, reset, inst_name_log ):
"""
Inserts an nf10_axis_sim core with provided arguments.
"""
if width is None:
width = ''
else:
width = 'PARAMETER C_M_AXIS_DATA_WIDTH = %s\n' % width
mhs[index:index] = mhstools.parse_mhs( cStringIO.StringIO( """\
#
# %s
BEGIN nf10_axis_sim_stim
PARAMETER INSTANCE = %s
PARAMETER HW_VER = %s
PARAMETER input_file = %s
%s\
BUS_INTERFACE M_AXIS = %s
PORT aclk = %s
PORT aresetn = %s
PORT counter = %s_counter
PORT activity_stim = %s_activity_stim
PORT barrier_req = %s_barrier_req
PORT barrier_proceed = nf10_barrier_0_barrier_proceed
END
""" % (comment, inst_name, ver, axi_file, width, net, clock, reset, inst_name_log, inst_name, inst_name) ) )
def insert_barrier(mhs, index):
mhs[index:index] = mhstools.parse_mhs(cStringIO.StringIO(
"""\
# BARRIER
BEGIN nf10_barrier
PARAMETER INSTANCE = nf10_barrier_0
PARAMETER HW_VER = 1.00.a
PORT activity_stim = %s
PORT activity_rec = %s
PORT activity_trans_sim = nf10_axi_sim_transactor_0_activity_trans_sim
PORT activity_trans_log = nf10_axi_sim_transactor_0_activity_trans_log
PORT barrier_req = %s
PORT barrier_req_trans = nf10_axi_sim_transactor_0_barrier_req_trans
PORT barrier_proceed = nf10_barrier_0_barrier_proceed
END
# TRANSACTOR
BEGIN nf10_axi_sim_transactor
PARAMETER INSTANCE = nf10_axi_sim_transactor_0
PARAMETER HW_VER = 1.10.a
BUS_INTERFACE M_AXI = axi_interconnect_0
PORT M_AXI_ARESETN = Peripheral_aresetn
PORT M_AXI_ACLK = control_clk
PORT activity_trans_sim = nf10_axi_sim_transactor_0_activity_trans_sim
PORT activity_trans_log = nf10_axi_sim_transactor_0_activity_trans_log
PORT barrier_req_trans = nf10_axi_sim_transactor_0_barrier_req_trans
PORT barrier_proceed = nf10_barrier_0_barrier_proceed
END
""" %(result_1, result, result_2)))
def scan_projects( projects_dir ):
"""
Generator function that walks projects directory and, for each project,
yields a tuple: (project_path, mhs)
"""
for root, dirs, files in os.walk( projects_dir ):
project = root[len(projects_dir)+1:]
# Get MHS file name, if any. There must be either exactly zero or one
# MHS file per project directory.
mhs_files = filter( lambda x: x.endswith( '.mhs' ), files )
if len( mhs_files ) == 0:
continue
if len( mhs_files ) > 1:
raise RuntimeError( (project, 'ambiguous (more than one) MHS files' ) )
# Parse and return MHS entities
with open( os.path.join( root, mhs_files[0] ) ) as mhs_fh:
mhs = mhstools.parse_mhs( mhs_fh )
yield (project, mhs)
def insert_recorder(mhs, index, comment, inst_name, ver, axi_file, width, net,
clock):
"""
Inserts an nf10_axis_sim core with provided arguments.
"""
if width is None:
width = ''
else:
width = 'PARAMETER C_S_AXIS_DATA_WIDTH = %s\n' % width
mhs[index:index] = mhstools.parse_mhs(
cStringIO.StringIO("""\
#
# %s
BEGIN nf10_axis_sim_record
PARAMETER INSTANCE = %s
PARAMETER HW_VER = %s
PARAMETER output_file = %s
%s\
BUS_INTERFACE S_AXIS = %s
PORT aclk = %s
END
""" % (comment, inst_name, ver, axi_file, width, net, clock)))
def main():
# Hackish but simple fix to optparser's annoying default behaviour of
# stripping newlines from the epilog.
optparse.OptionParser.format_epilog = lambda self, formatter: self.epilog
# Build and parse options
parser = optparse.OptionParser(
usage = '%prog [options] -m <input.mhs> [target_pcores ...]',
version= '1.0',
epilog = """
NB: A clock or reset net override not constrained to a specific instance or
type of pcore (eg -r =my_reset) forces respective net on ALL target
instances.
NB: if --mhs-out not specified, input MHS file will be substituted in-place.
Current list of default target pcores:
%s
""" % '\n\t'.join( DEFAULT_TARGETS )
)
parser.add_option(
'--undo', action='store_true', default=False,
help='Undo any previous substitution')
parser.add_option(
'-i', '--mhs-in', type='string', metavar='FILE',
help='Input MHS file')
parser.add_option(
'-o', '--mhs-out', type='string', metavar='FILE',
help='Output MHS file')
parser.add_option(
'-r', '--reset', type='string', metavar='[INST|CORE]=NET', dest='resets', default={},
action='callback', callback=net_override_cb, nargs=1, callback_args=(True,),
help='Override reset net for targets')
parser.add_option(
'-c', '--clock', type='string', metavar='[INST|CORE]=NET', dest='clocks', default={},
action='callback', callback=net_override_cb, nargs=1, callback_args=(True,),
help='Override clock net for targets')
parser.add_option(
'-x', '--xlate', type='string', metavar='NET=NET', dest='xlate', default={},
action='callback', callback=net_override_cb, nargs=1, callback_args=(False,),
help='Translate net names')
parser.add_option(
'-a', '--axi-path', type='string', metavar='PATH', default='../..',
help='Path to AXI files (default: ../../ which, from the simulator, means the project directory)')
parser.add_option(
'--no-default-targets', action='store_true', default=False,
help='Disable default list of target pcores for substitution')
opts, targets = parser.parse_args()
if opts.mhs_in is None:
raise parser.error( 'name of input MHS required' )
if not opts.no_default_targets:
targets += DEFAULT_TARGETS
# read and parse MHS file
with open( opts.mhs_in ) as mhs_fh:
mhs = mhstools.parse_mhs( mhs_fh )
# perform (or undo) substitutions
if opts.undo:
unsubst_mhs( mhs )
else:
if not subst_mhs( mhs, targets, opts ):
return 1
# write out MHS file
if opts.mhs_out is None:
os.rename( opts.mhs_in, os.path.splitext(opts.mhs_in)[0] + '.bk' )
opts.mhs_out = opts.mhs_in
with open( opts.mhs_out, 'w' ) as mhs_fh:
mhstools.write_mhs( mhs_fh, mhs )
return 0
def main():
# Hackish but simple fix to optparser's annoying default behaviour of
# stripping newlines from the epilog.
optparse.OptionParser.format_epilog = lambda self, formatter: self.epilog
# Build and parse options
parser = optparse.OptionParser(
usage="%prog [options] -m <input.mhs> [target_pcores ...]",
version="1.0",
epilog="""
NB: A clock or reset net override not constrained to a specific instance or
type of pcore (eg -r =my_reset) forces respective net on ALL target
instances.
NB: if --mhs-out not specified, input MHS file will be substituted in-place.
Current list of default target pcores:
%s
"""
% "\n\t".join(DEFAULT_TARGETS),
)
parser.add_option("--undo", action="store_true", default=False, help="Undo any previous substitution")
parser.add_option("-i", "--mhs-in", type="string", metavar="FILE", help="Input MHS file")
parser.add_option("-o", "--mhs-out", type="string", metavar="FILE", help="Output MHS file")
parser.add_option(
"-r",
"--reset",
type="string",
metavar="[INST|CORE]=NET",
dest="resets",
default={},
action="callback",
callback=net_override_cb,
nargs=1,
callback_args=(True,),
help="Override reset net for targets",
)
parser.add_option(
"-c",
"--clock",
type="string",
metavar="[INST|CORE]=NET",
dest="clocks",
default={},
action="callback",
callback=net_override_cb,
nargs=1,
callback_args=(True,),
help="Override clock net for targets",
)
parser.add_option(
"-x",
"--xlate",
type="string",
metavar="NET=NET",
dest="xlate",
default={},
action="callback",
callback=net_override_cb,
nargs=1,
callback_args=(False,),
help="Translate net names",
)
parser.add_option(
"-a",
"--axi-path",
type="string",
metavar="PATH",
default="../..",
help="Path to AXI files (default: ../../ which, from the simulator, means the project directory)",
)
parser.add_option(
"--no-default-targets",
action="store_true",
default=False,
help="Disable default list of target pcores for substitution",
)
opts, targets = parser.parse_args()
if opts.mhs_in is None:
raise parser.error("name of input MHS required")
if not opts.no_default_targets:
targets += DEFAULT_TARGETS
# read and parse MHS file
with open(opts.mhs_in) as mhs_fh:
mhs = mhstools.parse_mhs(mhs_fh)
# perform (or undo) substitutions
if opts.undo:
unsubst_mhs(mhs)
else:
if not subst_mhs(mhs, targets, opts):
return 1
# write out MHS file
if opts.mhs_out is None:
os.rename(opts.mhs_in, os.path.splitext(opts.mhs_in)[0] + ".bk")
opts.mhs_out = opts.mhs_in
with open(opts.mhs_out, "w") as mhs_fh:
mhstools.write_mhs(mhs_fh, mhs)
return 0
def main():
# Hackish but simple fix to optparser's annoying default behaviour of
# stripping newlines from the epilog.
optparse.OptionParser.format_epilog = lambda self, formatter: self.epilog
# Build and parse options
parser = optparse.OptionParser(
usage = '%prog [options] -m <input.mhs> [target_pcores ...]',
version= '1.0',
epilog = """
NB: A clock or reset net override not constrained to a specific instance or
type of pcore (eg -r =my_reset) forces respective net on ALL target
instances.
NB: if --mhs-out not specified, input MHS file will be substituted in-place.
Current list of default target pcores:
%s
""" % '\n\t'.join( DEFAULT_TARGETS )
)
parser.add_option(
'--undo', action='store_true', default=False,
help='Undo any previous substitution')
parser.add_option(
'-i', '--mhs-in', type='string', metavar='FILE',
help='Input MHS file')
parser.add_option(
'-o', '--mhs-out', type='string', metavar='FILE',
help='Output MHS file')
parser.add_option(
'-r', '--reset', type='string', metavar='[INST|CORE]=NET', dest='resets', default={},
action='callback', callback=net_override_cb, nargs=1, callback_args=(True,),
help='Override reset net for targets')
parser.add_option(
'-c', '--clock', type='string', metavar='[INST|CORE]=NET', dest='clocks', default={},
action='callback', callback=net_override_cb, nargs=1, callback_args=(True,),
help='Override clock net for targets')
parser.add_option(
'-x', '--xlate', type='string', metavar='NET=NET', dest='xlate', default={},
action='callback', callback=net_override_cb, nargs=1, callback_args=(False,),
help='Translate net names')
parser.add_option(
'-a', '--axi-path', type='string', metavar='PATH', default='../..',
help='Path to AXI files (default: ../../ which, from the simulator, means the project directory)')
parser.add_option(
'--no-default-targets', action='store_true', default=False,
help='Disable default list of target pcores for substitution')
opts, targets = parser.parse_args()
if opts.mhs_in is None:
raise parser.error( 'name of input MHS required' )
if not opts.no_default_targets:
targets += DEFAULT_TARGETS
# read and parse MHS file
with open( opts.mhs_in ) as mhs_fh:
mhs = mhstools.parse_mhs( mhs_fh )
# perform (or undo) substitutions
if opts.undo:
unsubst_mhs( mhs )
else:
if not subst_mhs( mhs, targets, opts ):
return 1
# write out MHS file
if opts.mhs_out is None:
os.rename( opts.mhs_in, os.path.splitext(opts.mhs_in)[0] + '.bk' )
opts.mhs_out = opts.mhs_in
with open( opts.mhs_out, 'w' ) as mhs_fh:
mhstools.write_mhs( mhs_fh, mhs )
return 0
