def __init__(self, name, **kwargs):
self.name = name
mkdir_noerror("build")
json.dump(kwargs, open("build/{}.json".format(name), "w"))
self.platform = platform = Platform()
kwargs["order"] = 2
x, y = [], []
iir = [IIR(**kwargs) for i in range(6)]
self.submodules += iir
c = Signal((flen(iir[0].x), True))
self.sync += c.eq(c + 1)
do = platform.request("do")
di = platform.request("di")
y = Array([0, 1, c, di, c + di, c - di, di + c, di - c] +
[iiri.y for iiri in iir])
muxi = Signal(max=len(y))
self.comb += do.eq(y[muxi])
self.sync += muxi.eq(c)
for i, iiri in enumerate(iir):
muxi = Signal(max=len(y))
self.sync += muxi.eq(c + i)
self.sync += iiri.x.eq(y[muxi])
self.sync += iiri.scale.eq(i * i - c - i)
self.sync += iiri.a[1].eq(-4 * c - 42341 + i)
self.sync += iiri.a[2].eq(2 * c + 33241 - i)
self.sync += iiri.b[0].eq(8 * c - 22323 + i)
self.sync += iiri.b[1].eq(c + 34094 - i)
self.sync += iiri.b[2].eq(4242 - 4 * c + i)
def build(self, platform, fragment, build_dir="build", build_name="top",
quartus_path="/opt/Altera", run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
v_output = platform.get_verilog(fragment)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")}
_build_files(platform.device,
sources,
platform.verilog_include_paths,
named_sc,
named_pc,
build_name)
if run:
_run_quartus(build_name, quartus_path)
os.chdir("..")
return v_output.ns
def build(self,
fragment,
build_dir="build",
build_name="top",
vivado_path="/opt/Xilinx/Vivado",
source=True,
run=True,
bitstream_compression=False):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, self.verilog_include_paths,
build_name, bitstream_compression)
tools.write_to_file(build_name + ".xdc",
_build_xdc(named_sc, named_pc))
if run:
_run_vivado(build_name, vivado_path, source)
os.chdir("..")
def build(self, platform, fragment, build_dir="build", build_name="top",
sim_path="../migen/mibuild/sim/", serial="console",
run=True, verbose=False):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
v_output = platform.get_verilog(fragment)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_output.write("dut.v")
include_paths = []
for source in platform.sources:
path = os.path.dirname(source[0]).replace("\\", "\/")
if path not in include_paths:
include_paths.append(path)
include_paths += platform.verilog_include_paths
_build_sim(platform, v_output.ns, build_name, include_paths, sim_path, serial, verbose)
if run:
_run_sim(build_name)
os.chdir("..")
return v_output.ns
def build(self, fragment, build_dir="build", build_name="top", ise_path="/opt/Xilinx", source=True, run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, named_sc, named_pc, build_name)
if run:
_run_ise(build_name, ise_path, source)
os.chdir("..")
def __init__(self, name, **kwargs):
self.name = name
mkdir_noerror("build")
json.dump(kwargs, open("build/{}.json".format(name), "w"))
self.platform = platform = Platform()
self.submodules.cordic = Cordic(**kwargs)
width = flen(self.cordic.xi)
self.comb += self.cordic.xi.eq(int((1 << width - 1) / self.cordic.gain * 0.98))
self.comb += self.cordic.yi.eq(0)
zi = self.cordic.zi
self.sync += zi.eq(zi + 1)
do = platform.request("do")
self.sync += do.eq(Cat(self.cordic.xo, self.cordic.yo))
def build(self,
fragment,
build_dir="build",
build_name="top",
ise_path="/opt/Xilinx",
source=True,
run=True,
mode="xst"):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
ngdbuild_opt = self.ngdbuild_opt
if mode == "xst" or mode == "yosys":
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
if mode == "xst":
_build_xst_files(self.device, sources,
self.verilog_include_paths, build_name,
self.xst_opt)
isemode = "xst"
else:
_run_yosys(self.device, sources, self.verilog_include_paths,
build_name)
isemode = "edif"
ngdbuild_opt += "-p " + self.device
if mode == "mist":
from mist import synthesize
synthesize(fragment, self.constraint_manager.get_io_signals())
if mode == "edif" or mode == "mist":
e_src, named_sc, named_pc = self.get_edif(fragment)
e_file = build_name + ".edif"
tools.write_to_file(e_file, e_src)
isemode = "edif"
tools.write_to_file(build_name + ".ucf",
_build_ucf(named_sc, named_pc))
if run:
_run_ise(build_name, ise_path, source, isemode, ngdbuild_opt,
self.bitgen_opt, self.ise_commands, self.map_opt,
self.par_opt)
os.chdir("..")
def __init__(self, name, **kwargs):
self.name = name
mkdir_noerror("build")
json.dump(kwargs, open("build/{}.json".format(name), "w"))
self.platform = platform = Platform()
self.submodules.cordic = Cordic(**kwargs)
width = flen(self.cordic.xi)
self.comb += self.cordic.xi.eq(
int((1 << width - 1) / self.cordic.gain * .98))
self.comb += self.cordic.yi.eq(0)
zi = self.cordic.zi
self.sync += zi.eq(zi + 1)
do = platform.request("do")
self.sync += do.eq(Cat(self.cordic.xo, self.cordic.yo))
def build(self, platform, fragment, build_dir="build", build_name="top",
ise_path=_default_ise_path(), source=_default_source(), run=True, mode="xst"):
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
ngdbuild_opt = self.ngdbuild_opt
vns = None
tools.mkdir_noerror(build_dir)
cwd = os.getcwd()
os.chdir(build_dir)
try:
if mode == "xst" or mode == "yosys":
v_output = platform.get_verilog(fragment)
vns = v_output.ns
named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v"
v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")}
if mode == "xst":
_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
isemode = "xst"
else:
_run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
isemode = "edif"
ngdbuild_opt += "-p " + platform.device
if mode == "mist":
from mist import synthesize
synthesize(fragment, platform.constraint_manager.get_io_signals())
if mode == "edif" or mode == "mist":
e_output = platform.get_edif(fragment)
vns = e_output.ns
named_sc, named_pc = platform.resolve_signals(vns)
e_file = build_name + ".edif"
e_output.write(e_file)
isemode = "edif"
tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
if run:
_run_ise(build_name, ise_path, source, isemode,
ngdbuild_opt, self.bitgen_opt, self.ise_commands,
self.map_opt, self.par_opt)
finally:
os.chdir(cwd)
return vns
def build(self, fragment, build_dir="build", build_name="top",
quartus_path="/opt/Altera", run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, self.verilog_include_paths, named_sc, named_pc, build_name)
if run:
_run_quartus(build_name, quartus_path)
os.chdir("..")
def build(self,
fragment,
build_dir="build",
build_name="top",
quartus_path="/opt/Altera",
run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, named_sc, named_pc, build_name)
if run:
_run_quartus(build_name, quartus_path)
os.chdir("..")
def build(self, fragment, build_dir="build", build_name="top",
vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, self.verilog_include_paths, build_name)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run:
_run_vivado(build_name, vivado_path, source)
os.chdir("..")
def build(self, fragment, build_dir="build", build_name="top",
ise_path="/opt/Xilinx", source=True, run=True, mode="xst"):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
ngdbuild_opt = self.ngdbuild_opt
if mode == "xst" or mode == "yosys":
v_src, named_sc, named_pc = self.get_verilog(fragment)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
if mode == "xst":
_build_xst_files(self.device, sources, self.verilog_include_paths, build_name, self.xst_opt)
isemode = "xst"
else:
_run_yosys(self.device, sources, self.verilog_include_paths, build_name)
isemode = "edif"
ngdbuild_opt += "-p " + self.device
if mode == "mist":
from mist import synthesize
synthesize(fragment, self.constraint_manager.get_io_signals())
if mode == "edif" or mode == "mist":
e_src, named_sc, named_pc = self.get_edif(fragment)
e_file = build_name + ".edif"
tools.write_to_file(e_file, e_src)
isemode = "edif"
tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
if run:
_run_ise(build_name, ise_path, source, isemode,
ngdbuild_opt, self.bitgen_opt, self.ise_commands,
self.map_opt, self.par_opt)
os.chdir("..")
def build(self, platform, fragment, build_dir="build", build_name="top",
vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
v_output = platform.get_verilog(fragment)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")}
self._build_batch(platform, sources, build_name)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run:
_run_vivado(build_name, vivado_path, source)
os.chdir("..")
return v_output.ns
