def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("""
TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns;
""")
try:
ifclk = self.lookup_request("fx2_ifclk")
gpif = self.lookup_request("fx2_gpif")
for i, d in [(gpif.d, "in"), (gpif.d, "out"),
(gpif.ctl, "in"), (gpif.adr, "out"),
(gpif.slwr, "out"), (gpif.sloe, "out"),
(gpif.slrd, "out"), (gpif.pktend, "out")]:
if flen(i) > 1:
q = "(*)"
else:
q = ""
self.add_platform_command("""
INST "{i}%s" TNM = gpif_net_%s;
""" % (q, d), i=i)
self.add_platform_command("""
NET "{ifclk}" TNM_NET = "GRPifclk";
TIMESPEC "TSifclk" = PERIOD "GRPifclk" 20833 ps HIGH 50%;
TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "{ifclk}" RISING;
TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "{ifclk}" RISING;
""", ifclk=ifclk)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("hdmi_in", 0).clk_p, 12)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("clk50", 0), 20)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(
self.lookup_request("hdmi_in", 0).clk_p, 12)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("clk50", 0), 20)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
eth_clocks = self.lookup_request("eth_clocks")
self.add_period_constraint(eth_clocks.rx, 40)
self.add_period_constraint(eth_clocks.tx, 40)
self.add_platform_command("""
TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
if isinstance(self.toolchain, XilinxISEToolchain):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
clk_if = self.lookup_request("clk_if")
clk_fx = self.lookup_request("clk_fx")
self.add_platform_command("""
NET "{clk_if}" TNM_NET = "GRPclk_if";
NET "{clk_fx}" TNM_NET = "GRPclk_fx";
TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%;
TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%;
TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY;
TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY;
""", clk_if=clk_if, clk_fx=clk_fx)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
for i in range(2):
try:
self.add_period_constraint(self.lookup_request("hdmi_in", i).clk_p, 12)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 40.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("fx2").ifclk, 20.8)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
for i in range(2):
try:
self.add_period_constraint(self.lookup_request("hdmi_in", i).clk_p, 12)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 40.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("fx2").ifclk, 20.8)
except ConstraintError:
pass
