def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
**kwargs)
self.csr_devices += ["spiflash", "ddrphy"]
self.submodules.crg = _CRG(platform)
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus, 16*1024*1024)
def main():
platform = kc705.Platform()
top = MicroscopeDemo(platform.request("serial"),
1e9 / platform.default_clk_period)
clock = platform.request(platform.default_clk_name)
top.submodules += CRG(clock)
platform.build(top)
def main():
platform = kc705.Platform()
top = ARTIQTTLRX(platform)
platform.build(top, build_dir="artiq_ttl_rx")
def build_rx():
platform = kc705.Platform()
top = PRBSRX(platform)
platform.build(top, build_dir="prbs_rx")
def build_tx():
platform = kc705.Platform()
top = PRBSTX(platform)
platform.build(top, build_dir="prbs_tx")
from misoc.cores.uart.core import RS232PHY
import wishbonebridge
class WBTest(Module):
def __init__(self, platform):
sys_clock_pads = platform.request("clk156")
self.clock_domains.cd_sys = ClockDomain(reset_less=True)
self.specials += Instance("IBUFGDS",
i_I=sys_clock_pads.p,
i_IB=sys_clock_pads.n,
o_O=self.cd_sys.clk)
self.submodules.phy = RS232PHY(platform.request("serial"), 156000000,
115200)
self.submodules.bridge = wishbonebridge.WishboneStreamingBridge(
self.phy, 156000000)
self.comb += [
self.bridge.wishbone.ack.eq(self.bridge.wishbone.cyc
& self.bridge.wishbone.stb),
self.bridge.wishbone.dat_r.eq(0xdeadbeef)
]
if __name__ == "__main__":
platform = kc705.Platform()
top = WBTest(platform)
platform.build(top, build_dir="wbtest")
def build_rx():
platform = kc705.Platform()
top = RemoteLEDRX(platform)
platform.build(top, build_dir="remote_led_rx")