def convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, return_ns=False, memory_handler=verilog_mem_behavioral.handler, display_run=False): if clk_signal is None: clk_signal = Signal(name_override="sys_clk") ios.add(clk_signal) if rst_signal is None: rst_signal = Signal(name_override="sys_rst") ios.add(rst_signal) ns = build_namespace(list_signals(f) \ | list_inst_ios(f, True, True, True) \ | list_mem_ios(f, True, True) \ | ios) r = "/* Machine-generated using Migen */\n" r += _printheader(f, ios, name, ns) r += _printcomb(f, ns, display_run) r += _printsync(f, ns, clk_signal, rst_signal) r += _printinstances(f, ns, clk_signal, rst_signal) r += _printmemories(f, ns, memory_handler, clk_signal) r += _printinit(f, ios, ns) r += "endmodule\n" if return_ns: return r, ns else: return r
def init(self, signals):
self.out_file = open(self.filename, "w")
# generate codes
for signal in signals:
try:
code = self.codes[signal]
except KeyError:
code = next(self.codegen)
self.codes[signal] = code
# write vcd header
header = ""
ns = build_namespace(self.codes.keys())
for signal, code in self.codes.items():
name = ns.get_name(signal)
header += "$var wire {len} {code} {name} $end\n".format(
name=name, code=code, len=len(signal))
header += "$dumpvars\n"
for signal in self.codes.keys():
header += self._write_value(signal, signal.reset.value)
header += "$end\n"
self.out_file.write(header)
if self.initialized:
self.buffer_file.seek(0)
shutil.copyfileobj(self.buffer_file, self.out_file)
self.buffer_file.seek(0, 2)
else:
# init time
self._write("#0\n")
self.initialized = True
def close(self):
out = open(self.filename, "w")
try:
if self.module_name:
out.write("$scope module {name} $end\n".format(name=self.module_name))
ns = build_namespace(self.codes.keys())
for signal, code in self.codes.items():
name = ns.get_name(signal)
if hasattr(signal, "_enumeration"):
size = max([len(v) for v in signal._enumeration.values()])*8
else:
size = len(signal)
out.write("$var wire {size} {code} {name} $end\n"
.format(name=name, code=code, size=size))
if self.module_name:
out.write("$enddefinitions $end\n")
out.write("$dumpvars\n")
for signal in self.codes.keys():
self._write_value(out, signal, signal.reset.value)
out.write("$end\n")
out.write("#0\n")
self.buffer_file.seek(0)
shutil.copyfileobj(self.buffer_file, out)
self.buffer_file.close()
finally:
out.close()
def convert(f,
ios=set(),
name="top",
clk_signal=None,
rst_signal=None,
return_ns=False,
memory_handler=verilog_mem_behavioral.handler,
display_run=False):
if clk_signal is None:
clk_signal = Signal(name_override="sys_clk")
ios.add(clk_signal)
if rst_signal is None:
rst_signal = Signal(name_override="sys_rst")
ios.add(rst_signal)
ns = build_namespace(list_signals(f) \
| list_inst_ios(f, True, True, True) \
| list_mem_ios(f, True, True) \
| ios)
r = "/* Machine-generated using Migen */\n"
r += _printheader(f, ios, name, ns)
r += _printcomb(f, ns, display_run)
r += _printsync(f, ns, clk_signal, rst_signal)
r += _printinstances(f, ns, clk_signal, rst_signal)
r += _printmemories(f, ns, memory_handler, clk_signal)
r += _printinit(f, ios, ns)
r += "endmodule\n"
if return_ns:
return r, ns
else:
return r
def convert(f, ios=None, name="top", clock_domains=None, return_ns=False, memory_handler=verilog_mem_behavioral.handler, display_run=False): if ios is None: ios = set() if clock_domains is None: clock_domains = dict() for d in f.get_clock_domains(): cd = ClockDomain(d) clock_domains[d] = cd ios.add(cd.clk) ios.add(cd.rst) f = lower_arrays(f) ns = build_namespace(list_signals(f) \ | list_inst_ios(f, True, True, True) \ | list_mem_ios(f, True, True) \ | ios) r = "/* Machine-generated using Migen */\n" r += _printheader(f, ios, name, ns) r += _printcomb(f, ns, display_run) r += _printsync(f, ns, clock_domains) r += _printinstances(f, ns, clock_domains) r += _printmemories(f, ns, memory_handler, clock_domains) r += _printinit(f, ios, ns) r += "endmodule\n" if return_ns: return r, ns else: return r
def convert(fi,
ios=None,
name="top",
special_overrides=dict(),
attr_translate=DummyAttrTranslate(),
create_clock_domains=True,
display_run=False):
r = ConvOutput()
f = _Fragment()
if not isinstance(fi, _Fragment):
fi = fi.get_fragment()
f += fi
if ios is None:
ios = set()
for cd_name in sorted(list_clock_domains(f)):
try:
f.clock_domains[cd_name]
except KeyError:
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
msg = "Available clock domains:\n"
for name in sorted(list_clock_domains(f)):
msg += "- " + name + "\n"
logging.error(msg)
raise KeyError("Unresolved clock domain: \"" + cd_name + "\"")
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
f, lowered_specials = lower_specials(special_overrides, f)
f = lower_basics(f)
for io in sorted(ios, key=lambda x: x.duid):
if io.name_override is None:
io_name = io.backtrace[-1][0]
if io_name:
io.name_override = io_name
ns = build_namespace(list_signals(f) \
| list_special_ios(f, True, True, True) \
| ios, _reserved_keywords)
ns.clock_domains = f.clock_domains
r.ns = ns
src = "/* Machine-generated using Migen */\n"
src += _printheader(f, ios, name, ns, attr_translate)
src += _printcomb(f, ns, display_run=display_run)
src += _printsync(f, ns)
src += _printspecials(special_overrides, f.specials - lowered_specials, ns,
r.add_data_file, attr_translate)
src += "endmodule\n"
r.set_main_source(src)
return r
def convert(fi, ios=None, name="top",
special_overrides=dict(),
attr_translate=DummyAttrTranslate(),
create_clock_domains=True,
display_run=False):
r = ConvOutput()
f = _Fragment()
if not isinstance(fi, _Fragment):
fi = fi.get_fragment()
f += fi
if ios is None:
ios = set()
for cd_name in sorted(list_clock_domains(f)):
try:
f.clock_domains[cd_name]
except KeyError:
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
msg = "Available clock domains:\n{}".format(
"\n".join("- {}".format(name)
for name in sorted(list_clock_domains(f))))
logging.error(msg)
raise KeyError("Unresolved clock domain: '{}'".format(cd_name))
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = lower_specials(special_overrides, f.specials)
f += lower_basics(fs)
for io in sorted(ios, key=hash):
if io.name_override is None:
io_name = io.backtrace[-1][0]
if io_name:
io.name_override = io_name
ns = build_namespace(
list_signals(f) | list_special_ios(f, True, True, True) | ios,
_reserved_keywords)
ns.clock_domains = f.clock_domains
r.ns = ns
src = "/* Machine-generated using Migen */\n"
src += _printheader(f, ios, name, ns, attr_translate)
src += _printcomb(f, ns, display_run=display_run)
src += _printsync(f, ns)
src += _printspecials(special_overrides, f.specials - lowered_specials,
ns, r.add_data_file, attr_translate)
src += "endmodule\n"
r.set_main_source(src)
return r
def convert(f, ios=None, name="top",
special_overrides=dict(),
attr_translate=DummyAttrTranslate(),
create_clock_domains=True,
display_run=False, asic_syntax=False):
r = ConvOutput()
if not isinstance(f, _Fragment):
f = f.get_fragment()
if ios is None:
ios = set()
for cd_name in sorted(list_clock_domains(f)):
try:
f.clock_domains[cd_name]
except KeyError:
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
raise KeyError("Unresolved clock domain: '"+cd_name+"'")
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = lower_specials(special_overrides, f.specials)
f += lower_basics(fs)
for io in sorted(ios, key=lambda x: x.duid):
if io.name_override is None:
io_name = io.backtrace[-1][0]
if io_name:
io.name_override = io_name
ns = build_namespace(list_signals(f) \
| list_special_ios(f, True, True, True) \
| ios, _reserved_keywords)
ns.clock_domains = f.clock_domains
r.ns = ns
src = "/* Machine-generated using Migen */\n"
src += _printheader(f, ios, name, ns, attr_translate,
reg_initialization=not asic_syntax)
src += _printcomb(f, ns,
display_run=display_run,
dummy_signal=not asic_syntax,
blocking_assign=asic_syntax)
src += _printsync(f, ns)
src += _printspecials(special_overrides, f.specials - lowered_specials,
ns, r.add_data_file, attr_translate)
src += "endmodule\n"
r.set_main_source(src)
return r
def convert(f, ios, cell_library, vendor, device, name="top", return_ns=False):
if not isinstance(f, _Fragment):
f = f.get_fragment()
if f.comb != [] or f.sync != {}:
raise ValueError("Edif conversion can only handle synthesized fragments")
if ios is None:
ios = set()
cells = _generate_cells(f)
ns = build_namespace(list_special_ios(f, True, True, True))
instances = _generate_instances(f, ns)
inouts = _generate_ios(f, ios, ns)
connections = _generate_connections(f, ios, ns)
r = _write_edif(cells, inouts, instances, connections, cell_library, name, device, vendor)
if return_ns:
return r, ns
else:
return r
def convert(f,
ios=None,
name="top",
return_ns=False,
special_overrides=dict(),
create_clock_domains=True,
display_run=False):
if not isinstance(f, _Fragment):
f = f.get_fragment()
if ios is None:
ios = set()
for cd_name in list_clock_domains(f):
try:
f.clock_domains[cd_name]
except KeyError:
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
raise KeyError("Unresolved clock domain: '" + cd_name + "'")
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = _lower_specials(special_overrides, f.specials)
f += lower_basics(fs)
ns = build_namespace(list_signals(f) \
| list_special_ios(f, True, True, True) \
| ios)
r = "/* Machine-generated using Migen */\n"
r += _printheader(f, ios, name, ns)
r += _printcomb(f, ns, display_run)
r += _printsync(f, ns)
r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
r += _printinit(f, ios, ns)
r += "endmodule\n"
if return_ns:
return r, ns
else:
return r
def close(self):
out = open(self.filename, "w")
try:
ns = build_namespace(self.codes.keys())
for signal, code in self.codes.items():
name = ns.get_name(signal)
out.write("$var wire {len} {code} {name} $end\n".format(name=name, code=code, len=len(signal)))
out.write("$dumpvars\n")
for signal in self.codes.keys():
self._write_value(out, signal, signal.reset.value)
out.write("$end\n")
out.write("#0\n")
self.buffer_file.seek(0)
shutil.copyfileobj(self.buffer_file, out)
self.buffer_file.close()
finally:
out.close()
def convert(f, ios, cell_library, vendor, device, name="top"):
if not isinstance(f, _Fragment):
f = f.get_fragment()
if f.comb != [] or f.sync != {}:
raise ValueError("EDIF conversion can only handle synthesized fragments")
if ios is None:
ios = set()
cells = _generate_cells(f)
ns = build_namespace(list_special_ios(f, True, True, True))
instances = _generate_instances(f, ns)
inouts = _generate_ios(f, ios, ns)
connections = _generate_connections(f, ios, ns)
src = _write_edif(cells, inouts, instances, connections, cell_library, name, device, vendor)
r = ConvOutput()
r.set_main_source(src)
r.ns = ns
return r
def convert(f,
ios=None,
name="top",
special_overrides=dict(),
attr_translate=None,
create_clock_domains=True,
display_run=False,
asic_syntax=False):
r = ConvOutput()
if R.complement(R.isinstance(_Fragment))(f):
f = f.get_fragment()
if ios is None:
ios = set()
for cd_name in sorted(list_clock_domains(f)):
try:
f.clock_domains[cd_name]
except KeyError:
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
raise KeyError("Unresolved clock domain: '{}'".format(cd_name))
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = lower_specials(special_overrides, f.specials)
f += lower_basics(fs)
ns = build_namespace(
list_signals(f) | list_special_ios(f, True, True, True) | ios,
_reserved_keywords)
ns.clock_domains = f.clock_domains
r.ns = ns
specials = f.specials - lowered_specials
r.set_main_source("".join([
_printentity(f, ios, name, ns),
_printarchitecture(f, ios, name, ns, special_overrides, specials,
r.add_data_file)
]))
return r
def convert(f, ios=None, name="top",
return_ns=False,
special_overrides=dict(),
create_clock_domains=True,
display_run=False):
if not isinstance(f, _Fragment):
f = f.get_fragment()
if ios is None:
ios = set()
for cd_name in list_clock_domains(f):
try:
f.clock_domains[cd_name]
except KeyError:
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
raise KeyError("Unresolved clock domain: '"+cd_name+"'")
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = _lower_specials(special_overrides, f.specials)
f += lower_basics(fs)
ns = build_namespace(list_signals(f) \
| list_special_ios(f, True, True, True) \
| ios)
r = "/* Machine-generated using Migen */\n"
r += _printheader(f, ios, name, ns)
r += _printcomb(f, ns, display_run)
r += _printsync(f, ns)
r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
r += _printinit(f, ios, ns)
r += "endmodule\n"
if return_ns:
return r, ns
else:
return r
def close(self):
out = open(self.filename, "w")
try:
ns = build_namespace(self.codes.keys())
for signal, code in self.codes.items():
name = ns.get_name(signal)
out.write("$var wire {len} {code} {name} $end\n".format(
name=name, code=code, len=len(signal)))
out.write("$dumpvars\n")
for signal in self.codes.keys():
self._write_value(out, signal, signal.reset.value)
out.write("$end\n")
out.write("#0\n")
self.buffer_file.seek(0)
shutil.copyfileobj(self.buffer_file, out)
self.buffer_file.close()
finally:
out.close()
def convert(f, ios, cell_library, vendor, device, name="top", return_ns=False):
if not isinstance(f, _Fragment):
f = f.get_fragment()
if f.comb != [] or f.sync != {}:
raise ValueError(
"Edif conversion can only handle synthesized fragments")
if ios is None:
ios = set()
cells = _generate_cells(f)
ns = build_namespace(list_special_ios(f, True, True, True))
instances = _generate_instances(f, ns)
inouts = _generate_ios(f, ios, ns)
connections = _generate_connections(f, ios, ns)
r = _write_edif(cells, inouts, instances, connections, cell_library, name,
device, vendor)
if return_ns:
return r, ns
else:
return r
def convert(f, ios, cell_library, vendor, device, name="top"):
if not isinstance(f, _Fragment):
f = f.get_fragment()
if f.comb != [] or f.sync != {}:
raise ValueError(
"EDIF conversion can only handle synthesized fragments")
if ios is None:
ios = set()
cells = _generate_cells(f)
ns = build_namespace(list_special_ios(f, True, True, True))
instances = _generate_instances(f, ns)
inouts = _generate_ios(f, ios, ns)
connections = _generate_connections(f, ios, ns)
src = _write_edif(cells, inouts, instances, connections, cell_library,
name, device, vendor)
r = ConvOutput()
r.set_main_source(src)
r.ns = ns
return r
def convert(f, ios=None, name="top",
special_overrides=dict(),
attr_translate=None,
create_clock_domains=True,
display_run=False,
asic_syntax=False):
r = ConvOutput()
if R.complement(R.isinstance(_Fragment))(f):
f = f.get_fragment()
if ios is None:
ios = set()
for cd_name in sorted(list_clock_domains(f)):
try:
f.clock_domains[cd_name]
except KeyError:
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
raise KeyError("Unresolved clock domain: '{}'".format(cd_name))
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = lower_specials(special_overrides, f.specials)
f += lower_basics(fs)
ns = build_namespace(
list_signals(f) | list_special_ios(f, True, True, True) | ios,
_reserved_keywords)
ns.clock_domains = f.clock_domains
r.ns = ns
specials = f.specials - lowered_specials
r.set_main_source("".join([
_printentity(f, ios, name, ns),
_printarchitecture(
f, ios, name, ns, special_overrides, specials, r.add_data_file)]))
return r
def close(self):
out = open(self.filename, "w")
try:
ns = build_namespace(self.codes.keys())
for signal, code in self.codes.items():
name = ns.get_name(signal)
if hasattr(signal, "_enumeration"):
size = max([len(v) for v in signal._enumeration.values()]) * 8
else:
size = len(signal)
out.write("$var wire {size} {code} {name} $end\n"
.format(name=name, code=code, size=size))
out.write("$dumpvars\n")
for signal in self.codes.keys():
self._write_value(out, signal, signal.reset.value)
out.write("$end\n")
out.write("#0\n")
self.buffer_file.seek(0)
shutil.copyfileobj(self.buffer_file, out)
self.buffer_file.close()
finally:
out.close()
def convert(f, ios=None, name="top", clock_domains=None, return_ns=False, special_overrides=dict(), display_run=False): if ios is None: ios = set() if clock_domains is None: clock_domains = dict() for d in list_clock_domains(f): cd = ClockDomain(d) clock_domains[d] = cd ios.add(cd.clk) ios.add(cd.rst) f = lower_arrays(f) fs, lowered_specials = _lower_specials(special_overrides, f.specials) f += fs _insert_resets(f, clock_domains) ns = build_namespace(list_signals(f) \ | list_special_ios(f, True, True, True) \ | ios) r = "/* Machine-generated using Migen */\n" r += _printheader(f, ios, name, ns) r += _printcomb(f, ns, display_run) r += _printsync(f, ns, clock_domains) r += _printspecials(special_overrides, f.specials - lowered_specials, ns, clock_domains) r += _printinit(f, ios, ns) r += "endmodule\n" if return_ns: return r, ns else: return r
def convert(f, ios=set(), name="top", platform=None,
special_overrides = dict(),
attr_translate = DummyAttrTranslate(),
regular_comb = True):
# Create ConvOutput.
r = ConvOutput()
# Convert to FHDL's fragments is not already done.
if not isinstance(f, _Fragment):
f = f.get_fragment()
# Verify/Create Clock Domains.
for cd_name in sorted(list_clock_domains(f)):
# Try to get Clock Domain.
try:
f.clock_domains[cd_name]
# If not found, raise Error.
except:
msg = f"""Unresolved clock domain {cd_name}, availables:\n"""
for f in f.clock_domains:
msg += f"- {f.name}\n"
raise Exception(msg)
# Lower complex slices.
f = lower_complex_slices(f)
# Insert resets.
insert_resets(f)
# Lower basics.
f = lower_basics(f)
# Lower specials.
if platform is not None:
for s in f.specials:
s.platform = platform
f, lowered_specials = lower_specials(special_overrides, f)
# Lower basics (for basics included in specials).
f = lower_basics(f)
# IOs collection (when not specified).
if len(ios) == 0:
assert platform is not None
ios = platform.constraint_manager.get_io_signals()
# IOs backtrace/naming.
for io in sorted(ios, key=lambda x: x.duid):
if io.name_override is None:
io_name = io.backtrace[-1][0]
if io_name:
io.name_override = io_name
# Build NameSpace.
# ----------------
ns = build_namespace(
signals = (
list_signals(f) |
list_special_ios(f, ins=True, outs=True, inouts=True) |
ios),
reserved_keywords = _ieee_1800_2017_verilog_reserved_keywords
)
ns.clock_domains = f.clock_domains
# Build Verilog.
# --------------
verilog = ""
verilog += _print_banner(
filename = name,
device = getattr(platform, "device", "Unknown")
)
# Module Definition.
verilog += _print_separator("Module")
verilog += _print_module(f, ios, name, ns, attr_translate)
# Module Signals.
verilog += _print_separator("Signals")
verilog += _print_signals(f, ios, name, ns, attr_translate)
# Combinatorial Logic.
verilog += _print_separator("Combinatorial Logic")
if regular_comb:
verilog += _print_combinatorial_logic_synth(f, ns)
else:
verilog += _print_combinatorial_logic_sim(f, ns)
# Synchronous Logic.
verilog += _print_separator("Synchronous Logic")
verilog += _print_synchronous_logic(f, ns)
# Specials
verilog += _print_separator("Specialized Logic")
verilog += _print_specials(special_overrides, f.specials - lowered_specials,
ns, r.add_data_file, attr_translate)
# Module End.
verilog += "endmodule\n"
verilog += _print_trailer()
r.set_main_source(verilog)
r.ns = ns
return r
def convert(f,
ios=None,
name="top",
special_overrides=dict(),
attr_translate=DummyAttrTranslate(),
create_clock_domains=True,
display_run=False,
reg_initialization=True,
dummy_signal=True,
blocking_assign=False,
regular_comb=True):
r = ConvOutput()
if not isinstance(f, _Fragment):
f = f.get_fragment()
if ios is None:
ios = set()
for cd_name in sorted(list_clock_domains(f)):
try:
f.clock_domains[cd_name]
except KeyError:
if create_clock_domains:
cd = ClockDomain(cd_name)
f.clock_domains.append(cd)
ios |= {cd.clk, cd.rst}
else:
print("available clock domains:")
for f in f.clock_domains:
print(f.name)
raise KeyError("Unresolved clock domain: '" + cd_name + "'")
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = lower_specials(special_overrides, f.specials)
f += lower_basics(fs)
for io in sorted(ios, key=lambda x: x.duid):
if io.name_override is None:
io_name = io.backtrace[-1][0]
if io_name:
io.name_override = io_name
ns = build_namespace(list_signals(f) \
| list_special_ios(f, True, True, True) \
| ios, _reserved_keywords)
ns.clock_domains = f.clock_domains
r.ns = ns
src = "/* Machine-generated using LiteX gen */\n"
src += _printheader(f,
ios,
name,
ns,
attr_translate,
reg_initialization=reg_initialization)
if regular_comb:
src += _printcomb_regular(f, ns, blocking_assign=blocking_assign)
else:
src += _printcomb_simulation(f,
ns,
display_run=display_run,
dummy_signal=dummy_signal,
blocking_assign=blocking_assign)
src += _printsync(f, ns)
src += _printspecials(special_overrides, f.specials - lowered_specials, ns,
r.add_data_file, attr_translate)
src += "endmodule\n"
r.set_main_source(src)
return r