def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts): if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() if top_level is None: top_level = TopLevel() if sim_runner is None: sim_runner = icarus.Runner() self.top_level = top_level self.ipc = Initiator(sockaddr) self.sim_runner = sim_runner c_top = self.top_level.get(sockaddr) fragment = fragment + _Fragment(clock_domains=top_level.clock_domains) c_fragment, self.namespace = verilog.convert(fragment, ios=self.top_level.ios, name=self.top_level.dut_type, return_ns=True, **vopts) self.cycle_counter = -1 self.sim_runner = sim_runner self.sim_runner.start(c_top, c_fragment) self.ipc.accept() reply = self.ipc.recv() assert(isinstance(reply, MessageTick)) self.sim_functions = fragment.sim self.active_sim_functions = set(f for f in fragment.sim if not hasattr(f, "passive") or not f.passive)
def _inner_setup(self): # Verify that all necessary files are present files = gather_files(self.tb) for i in files: if not os.path.exists(i): raise FileNotFoundError( "Please download and save the vendor " "SDRAM model in %s (not redistributable)" % i) runner = icarus.Runner(extra_files=files) self.sim = Simulator(self.tb, sim_runner=runner)
def setUp(self): self.tb = TestBench("mt48lc16m16a2") # Verify that all necessary files are present files = gather_files(self.tb) for i in files: if not os.path.exists(i): raise FileNotFoundError("Please download and save the vendor " "SDRAM model in %s (not redistributable)" % i) runner = icarus.Runner(extra_files=files) vcd = "test_%s.vcd" % self.__class__.__name__ self.sim = Simulator(self.tb, TopLevel(vcd), sim_runner=runner)
# stop bit selfp.pads.rx = 1 elif (i == 10): selfp.pads.rx = 1 break else: selfp.pads.rx = 1 if (rx_value & 1) else 0 rx_value >>= 1 yield from self.wait_for(uart_period) rx_value = ord(rx_string) received_value = selfp.slave._r_rxtx.w if (received_value == rx_value): print("RX SUCCESS: ") else: print("RX FAILURE: ") print("received " + chr(received_value)) while True: yield if __name__ == "__main__": from migen.sim.generic import Simulator, TopLevel from migen.sim import icarus with Simulator(UARTTB(), TopLevel("top.vcd", clk_period=int(1 / 0.08333333)), icarus.Runner(keep_files=False)) as s: s.run(20000)
tRP=ns(15), tRCD=ns(15), tWR=ns(14), tWTR=2, tREFI=ns(64*1000*1000/4096, False), tRFC=ns(66), req_queue_size=8, read_time=32, write_time=16 ) sdram_pads = plat.request("sdram") sdram_clk = plat.request("sdram_clock") sdrphy = gensdrphy.GENSDRPHY(sdram_pads) # This sets CL to 2 during LMR done on 1st cycle sdram_pads.a.reset = 1<<5 s = MiniconTB(sdrphy, sdrphy.dfi, sdram_geom, sdram_timing, pads=sdram_pads, sdram_clk=sdram_clk) extra_files = ["sdram_model/mt48lc4m16a2.v"] if not isfile(extra_files[0]): print("ERROR: You need to download Micron Verilog simulation model for MT48LC4M16A2 and put it in sdram_model/mt48lc4m16a2.v") print("File can be downloaded from this URL: http://www.micron.com/-/media/documents/products/sim%20model/dram/dram/4054mt48lc4m16a2.zip") sys.exit(1) with Simulator(s, MyTopLevel("top.vcd", clk_period=int(1/0.08)), icarus.Runner(extra_files=extra_files, keep_files=True)) as sim: sim.run(5000)
sdram_pads = plat.request("sdram") sdram_clk = plat.request("sdram_clock") sdrphy = gensdrphy.GENSDRPHY(sdram_pads) # This sets CL to 2 during LMR done on 1st cycle sdram_pads.a.reset = 1 << 5 s = MiniconTB(sdrphy, sdrphy.dfi, sdram_geom, sdram_timing, pads=sdram_pads, sdram_clk=sdram_clk) extra_files = ["sdram_model/mt48lc4m16a2.v"] if not isfile(extra_files[0]): print( "ERROR: You need to download Micron Verilog simulation model for MT48LC4M16A2 and put it in sdram_model/mt48lc4m16a2.v" ) print( "File can be downloaded from this URL: http://www.micron.com/-/media/documents/products/sim%20model/dram/dram/4054mt48lc4m16a2.zip" ) sys.exit(1) with Simulator(s, MyTopLevel("top.vcd", clk_period=int(1 / 0.08)), icarus.Runner(extra_files=extra_files, keep_files=True)) as sim: sim.run(5000)
def run_simulation(fragment, ncycles=None, vcd_name=None, keep_files=False): with Simulator(fragment, TopLevel(vcd_name), icarus.Runner(keep_files=keep_files)) as s: s.run(ncycles)
def run_simulation(fragment, ncycles=None, vcd_name=None, **kwargs): with Simulator(fragment, TopLevel(vcd_name), icarus.Runner(**kwargs)) as s: s.run(ncycles)