def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs): BaseSoC.__init__(self, *args, **kwargs) self.create_qpll() self.csr_devices += ["ethphy", "ethmac"] self.interrupt_devices.append("ethmac") sfp = self.platform.request("sfp", 0) self.submodules.ethphy = A7_1000BASEX(self.ethphy_qpll_channel, sfp, self.clk_freq) self.platform.add_period_constraint(self.ethphy.txoutclk, 16.) self.platform.add_period_constraint(self.ethphy.rxoutclk, 16.) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.txoutclk, self.ethphy.rxoutclk) sfp_ctl = self.platform.request("sfp_ctl", 0) self.comb += [ sfp_ctl.rate_select.eq(0), sfp_ctl.tx_disable.eq(0), sfp_ctl.led.eq(~sfp_ctl.los & ~sfp_ctl.tx_fault & sfp_ctl.mod_present & self.ethphy.link_up), ] self.submodules.ethmac = LiteEthMAC( phy=self.ethphy, dw=32, interface="wishbone", nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots) ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800 self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, ethmac_len)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs): BaseSoC.__init__(self, *args, **kwargs) self.create_qpll() self.csr_devices += ["ethphy", "ethmac"] self.interrupt_devices.append("ethmac") self.submodules.ethphy = A7_1000BASEX( self.ethphy_qpll_channel, self.platform.request("mgt113", 3), self.clk_freq) self.platform.add_period_constraint(self.ethphy.txoutclk, 16.) self.platform.add_period_constraint(self.ethphy.rxoutclk, 16.) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.txoutclk, self.ethphy.rxoutclk) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=self.cpu_dw, interface="wishbone", endianness=self.cpu.endianness, nrxslots=2, ntxslots=2) ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800 self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, ethmac_len)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, ethphy_qpll_channel=None, **kwargs): BaseSoC.__init__(self, *args, **kwargs) self.csr_devices += ["ethphy", "ethmac"] self.interrupt_devices.append("ethmac") sfp = self.platform.request("sfp", 0) self.comb += [ sfp.rate_select.eq(1), sfp.tx_disable.eq(0), ] if ethphy_qpll_channel is None: clk125 = self.platform.request("clk125_gtp") clk125_buf = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=0, i_I=clk125.p, i_IB=clk125.n, o_O=clk125_buf) qpll_settings = QPLLSettings(refclksel=0b001, fbdiv=4, fbdiv_45=5, refclk_div=1) qpll = QPLL(clk125_buf, qpll_settings) self.submodules += qpll ethphy_qpll_channel = qpll.channels[0] sfp = self.platform.request("sfp_gtp", 0) self.submodules.ethphy = A7_1000BASEX(ethphy_qpll_channel, sfp, self.clk_freq) self.platform.add_period_constraint(self.ethphy.txoutclk, 16e-9) self.platform.add_period_constraint(self.ethphy.rxoutclk, 16e-9) self.platform.add_period_constraint(self.crg.cd_sys.clk, self.clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.txoutclk, self.ethphy.rxoutclk) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots) ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800 self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, ethmac_len)