def main(): parser = argparse.ArgumentParser( description="Sayma RTM gateware builder") parser.add_argument("--hw-rev", default="v1.0", help="Sayma RTM hardware revision: v1.0/v2.0") parser.add_argument("--output-dir", default="artiq_sayma/rtm_gateware", help="output directory for generated " "source files and binaries") parser.add_argument("--no-compile-gateware", action="store_true", help="do not compile the gateware, only generate " "the CSR map") parser.add_argument("--csr-csv", default=None, help="store CSR map in CSV format into the " "specified file") args = parser.parse_args() platform_module = { "v1.0": sayma_rtm, "v2.0": sayma_rtm2 }[args.hw_rev] platform = platform_module.Platform() top = SaymaRTM(platform, args.hw_rev) os.makedirs(args.output_dir, exist_ok=True) with open(os.path.join(args.output_dir, "rtm_csr.csv"), "w") as f: f.write(get_csr_csv(top.csr_regions)) if not args.no_compile_gateware: platform.build(top, build_dir=args.output_dir, build_name="rtm")
def main(): parser = argparse.ArgumentParser( description="ARTIQ device binary builder for Kasli systems") parser.add_argument("--output-dir", default="artiq_sayma/rtm_gateware", help="output directory for generated " "source files and binaries") parser.add_argument("--no-compile-gateware", action="store_true", help="do not compile the gateware, only generate " "the CSR map") parser.add_argument("--csr-csv", default=None, help="store CSR map in CSV format into the " "specified file") args = parser.parse_args() platform = sayma_rtm.Platform() top = SaymaRTM(platform) os.makedirs(args.output_dir, exist_ok=True) with open(os.path.join(args.output_dir, "rtm_csr.csv"), "w") as f: f.write(get_csr_csv(top.csr_regions)) if not args.no_compile_gateware: platform.build(top, build_dir=args.output_dir, build_name="rtm")
def _generate_includes(self): cpu_type = self.soc.cpu_type memory_regions = self.soc.get_memory_regions() memory_groups = self.soc.get_memory_groups() flash_boot_address = getattr(self.soc, "flash_boot_address", None) csr_regions = self.soc.get_csr_regions() csr_groups = self.soc.get_csr_groups() constants = self.soc.get_constants() if isinstance(self.soc, soc_sdram.SoCSDRAM) and self.soc._sdram_phy: sdram_phy_settings = self.soc._sdram_phy[0].settings else: sdram_phy_settings = None buildinc_dir = os.path.join(self.output_dir, "software", "include") generated_dir = os.path.join(buildinc_dir, "generated") os.makedirs(generated_dir, exist_ok=True) with WriteGenerated(generated_dir, "variables.mak") as f: def define(k, v): f.write("{}={}\n".format(k, _makefile_escape(v))) for k, v in cpu_interface.get_cpu_mak(cpu_type): define(k, v) define("MISOC_DIRECTORY", misoc_directory) define("BUILDINC_DIRECTORY", buildinc_dir) f.write("export BUILDINC_DIRECTORY\n") for name, src_dir in self.software_packages: define(name.upper() + "_DIRECTORY", src_dir) with WriteGenerated(generated_dir, "output_format.ld") as f: f.write(cpu_interface.get_linker_output_format(cpu_type)) with WriteGenerated(generated_dir, "regions.ld") as f: f.write(cpu_interface.get_linker_regions(memory_regions)) with WriteGenerated(generated_dir, "mem.h") as f: f.write( cpu_interface.get_mem_header(memory_regions, flash_boot_address)) with WriteGenerated(generated_dir, "csr.h") as f: f.write(cpu_interface.get_csr_header(csr_regions, constants)) with WriteGenerated(generated_dir, "mem.rs") as f: f.write( cpu_interface.get_mem_rust(memory_regions, memory_groups, flash_boot_address)) with WriteGenerated(generated_dir, "csr.rs") as f: f.write( cpu_interface.get_csr_rust(csr_regions, csr_groups, constants)) with WriteGenerated(generated_dir, "rust-cfg") as f: f.write(cpu_interface.get_rust_cfg(csr_regions, constants)) if sdram_phy_settings is not None: with WriteGenerated(generated_dir, "sdram_phy.h") as f: f.write(sdram_init.get_sdram_phy_header(sdram_phy_settings)) if self.csr_csv is not None: with open(self.csr_csv, "w") as f: f.write(cpu_interface.get_csr_csv(csr_regions))
def main(): build_dir = "artiq_sayma_rtm" platform = sayma_rtm.Platform() top = SaymaRTM(platform) os.makedirs(build_dir, exist_ok=True) with open(os.path.join(build_dir, "sayma_rtm_csr.csv"), "w") as f: f.write(get_csr_csv(top.csr_regions)) platform.build(top, build_dir=build_dir)
def generate_includes(self): cpu_type = self.soc.cpu_type memory_regions = self.soc.get_memory_regions() memory_groups = self.soc.get_memory_groups() flash_boot_address = getattr(self.soc, "flash_boot_address", None) csr_regions = self.soc.get_csr_regions() csr_groups = self.soc.get_csr_groups() constants = self.soc.get_constants() if isinstance(self.soc, soc_sdram.SoCSDRAM) and self.soc._sdram_phy: sdram_phy_settings = self.soc._sdram_phy[0].settings else: sdram_phy_settings = None buildinc_dir = os.path.join(self.output_dir, "software", "include") generated_dir = os.path.join(buildinc_dir, "generated") os.makedirs(generated_dir, exist_ok=True) with WriteGenerated(generated_dir, "variables.mak") as f: def define(k, v): f.write("{}={}\n".format(k, _makefile_escape(v))) for k, v in cpu_interface.get_cpu_mak(cpu_type): define(k, v) define("MISOC_DIRECTORY", misoc_directory) define("BUILDINC_DIRECTORY", buildinc_dir) f.write("export BUILDINC_DIRECTORY\n") for name, src_dir in self.software_packages: define(name.upper() + "_DIRECTORY", src_dir) with WriteGenerated(generated_dir, "output_format.ld") as f: f.write(cpu_interface.get_linker_output_format(cpu_type)) with WriteGenerated(generated_dir, "regions.ld") as f: f.write(cpu_interface.get_linker_regions(memory_regions)) with WriteGenerated(generated_dir, "mem.h") as f: f.write(cpu_interface.get_mem_header(memory_regions, flash_boot_address)) with WriteGenerated(generated_dir, "csr.h") as f: f.write(cpu_interface.get_csr_header(csr_regions, constants)) with WriteGenerated(generated_dir, "mem.rs") as f: f.write(cpu_interface.get_mem_rust(memory_regions, memory_groups, flash_boot_address)) with WriteGenerated(generated_dir, "csr.rs") as f: f.write(cpu_interface.get_csr_rust(csr_regions, csr_groups, constants)) with WriteGenerated(generated_dir, "rust-cfg") as f: f.write(cpu_interface.get_rust_cfg(csr_regions, constants)) if sdram_phy_settings is not None: with WriteGenerated(generated_dir, "sdram_phy.h") as f: f.write(sdram_init.get_sdram_phy_header(sdram_phy_settings)) with WriteGenerated(generated_dir, "sdram_phy.rs") as f: f.write(sdram_init.get_sdram_phy_rust(sdram_phy_settings)) if self.csr_csv is not None: with open(self.csr_csv, "w") as f: f.write(cpu_interface.get_csr_csv(csr_regions))
def main(): parser = argparse.ArgumentParser( description="ARTIQ device binary builder for Kasli systems") parser.add_argument("--output-dir", default="artiq_sayma/rtm_gateware", help="output directory for generated " "source files and binaries") parser.add_argument("--no-compile-gateware", action="store_true", help="do not compile the gateware, only generate " "the CSR map") parser.add_argument("--csr-csv", default=None, help="store CSR map in CSV format into the " "specified file") args = parser.parse_args() platform = sayma_rtm.Platform() top = SaymaRTM(platform) os.makedirs(args.output_dir, exist_ok=True) with open(os.path.join(args.output_dir, "rtm_csr.csv"), "w") as f: f.write(get_csr_csv(top.csr_regions)) if not args.no_compile_gateware: platform.build(top, build_dir=args.output_dir, build_name="rtm")
def _export_register_addresses(self): with (self.build_path / "csr.csv").open("w") as f: f.write(cpu_interface.get_csr_csv(self.soc.get_csr_regions()))