def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big"):
self.sink = stream.Endpoint(eth_phy_layout(dw))
self.source = stream.Endpoint(eth_phy_layout(dw))
self.bus = wishbone.Interface(data_width=dw, adr_width=32-log2_int(dw//8))
# # #
# storage in SRAM
sram_depth = eth_mtu//(dw//8)
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness)
self.comb += [
self.sink.connect(self.sram.sink),
self.sram.source.connect(self.source)
]
# Wishbone interface
wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True, data_width=dw)
for n in range(nrxslots)]
# TODO: FullMemoryWE should move to Mibuild
wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False, data_width=dw))
for n in range(ntxslots)]
wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
wb_slaves = []
decoderoffset = log2_int(sram_depth, need_pow2=False)
decoderbits = log2_int(len(wb_sram_ifs))
for n, wb_sram_if in enumerate(wb_sram_ifs):
def slave_filter(a, v=n):
return a[decoderoffset:decoderoffset+decoderbits] == v
wb_slaves.append((slave_filter, wb_sram_if.bus))
self.submodules += wb_sram_if
wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
self.submodules += wb_con
def __init__(self, link_layer):
self.bus = wishbone.Interface()
self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w))
self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w))
tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False)
rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
wsb = log2_int(len(self.bus.dat_w)//8)
decoder = wishbone.Decoder(self.bus,
[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus),
(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)],
register=True)
self.submodules += tx_sdram_if, rx_sdram_if, decoder
def __init__(self, platform):
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])
csr_devices = []
self.submodules.crg = CRG(platform)
clk_freq = 125e6
self.submodules.rtm_identifier = RTMIdentifier()
csr_devices.append("rtm_identifier")
# clock mux: 100MHz ext SMA clock to HMC830 input
self.submodules.clock_mux = gpio.GPIOOut(Cat(
platform.request("clk_src_ext_sel"),
platform.request("ref_clk_src_sel"),
platform.request("dac_clk_src_sel")))
csr_devices.append("clock_mux")
# UART loopback
serial = platform.request("serial")
self.comb += serial.tx.eq(serial.rx)
# Allaki: enable RF output, GPIO access to attenuator
self.comb += [
platform.request("allaki0_rfsw0").eq(1),
platform.request("allaki0_rfsw1").eq(1),
platform.request("allaki1_rfsw0").eq(1),
platform.request("allaki1_rfsw1").eq(1),
platform.request("allaki2_rfsw0").eq(1),
platform.request("allaki2_rfsw1").eq(1),
platform.request("allaki3_rfsw0").eq(1),
platform.request("allaki3_rfsw1").eq(1),
]
allaki_atts = [
platform.request("allaki0_att0"),
platform.request("allaki0_att1"),
platform.request("allaki1_att0"),
platform.request("allaki1_att1"),
platform.request("allaki2_att0"),
platform.request("allaki2_att1"),
platform.request("allaki3_att0"),
platform.request("allaki3_att1"),
]
allaki_att_gpio = []
for allaki_att in allaki_atts:
allaki_att_gpio += [
allaki_att.le,
allaki_att.sin,
allaki_att.clk,
allaki_att.rst_n,
]
self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio))
csr_devices.append("allaki_atts")
# HMC clock chip and DAC control
self.comb += [
platform.request("ad9154_rst_n").eq(1),
platform.request("ad9154_txen", 0).eq(0b11),
platform.request("ad9154_txen", 1).eq(0b11)
]
self.submodules.converter_spi = spi.SPIMaster([
platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)])
csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0)
# AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(62.5e6, 625e6, vco_div=1)
self.submodules += serwb_pll
serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 16.)
serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += self.crg.reset.eq(serwb_phy_rtm.init.reset)
csr_devices.append("serwb_phy_rtm")
serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
serwb_phy_rtm.serdes.cd_serwb_serdes.clk,
serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk)
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True)
self.submodules += serwb_core
# process CSR devices and connect them to serwb
self.csr_regions = []
wb_slaves = WishboneSlaveManager(0x10000000)
for i, name in enumerate(csr_devices):
origin = i*CSR_RANGE_SIZE
module = getattr(self, name)
csrs = module.get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
self.csr_regions.append((name, origin, 32, csrs))
self.submodules += wishbone.Decoder(serwb_core.etherbone.wishbone.bus,
wb_slaves.get_interconnect_slaves(),
register=True)
def __init__(self, platform):
csr_devices = []
self.submodules.crg = CRG(platform)
clk_freq = 125e6
self.submodules.rtm_magic = RTMMagic()
csr_devices.append("rtm_magic")
self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
csr_devices.append("rtm_identifier")
# clock mux: 100MHz ext SMA clock to HMC830 input
self.submodules.clock_mux = gpio.GPIOOut(
Cat(platform.request("clk_src_ext_sel"),
platform.request("ref_clk_src_sel"),
platform.request("dac_clk_src_sel")))
csr_devices.append("clock_mux")
# UART loopback
serial = platform.request("serial")
self.comb += serial.tx.eq(serial.rx)
# Allaki: enable RF output, GPIO access to attenuator
self.comb += [
platform.request("allaki0_rfsw0").eq(1),
platform.request("allaki0_rfsw1").eq(1),
platform.request("allaki1_rfsw0").eq(1),
platform.request("allaki1_rfsw1").eq(1),
platform.request("allaki2_rfsw0").eq(1),
platform.request("allaki2_rfsw1").eq(1),
platform.request("allaki3_rfsw0").eq(1),
platform.request("allaki3_rfsw1").eq(1),
]
allaki_atts = [
platform.request("allaki0_att0"),
platform.request("allaki0_att1"),
platform.request("allaki1_att0"),
platform.request("allaki1_att1"),
platform.request("allaki2_att0"),
platform.request("allaki2_att1"),
platform.request("allaki3_att0"),
platform.request("allaki3_att1"),
]
allaki_att_gpio = []
for allaki_att in allaki_atts:
allaki_att_gpio += [
allaki_att.le,
allaki_att.sin,
allaki_att.clk,
allaki_att.rst_n,
]
self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio))
csr_devices.append("allaki_atts")
# HMC clock chip and DAC control
self.comb += [
platform.request("ad9154_rst_n").eq(1),
platform.request("ad9154_txen", 0).eq(0b11),
platform.request("ad9154_txen", 1).eq(0b11)
]
self.submodules.converter_spi = spi2.SPIMaster(
spi2.SPIInterface(platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0)
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 8.)
serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device,
serwb_pads,
mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += [
self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),
self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset)
]
csr_devices.append("serwb_phy_rtm")
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm,
int(clk_freq),
mode="master")
self.submodules += serwb_core
# process CSR devices and connect them to serwb
self.csr_regions = []
wb_slaves = WishboneSlaveManager(0x10000000)
for i, name in enumerate(csr_devices):
origin = i * CSR_RANGE_SIZE
module = getattr(self, name)
csrs = module.get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
self.csr_regions.append((name, origin, 32, csrs))
self.submodules += wishbone.Decoder(
serwb_core.etherbone.wishbone.bus,
wb_slaves.get_interconnect_slaves(),
register=True)
def __init__(self, platform, pads, **kwargs):
self.submodules.ll = ClockDomainsRenamer("local")(SDLinkLayer(
platform, pads, **kwargs))
# Event interrupts and acknowledgment
self.submodules.ev = EventManager()
self.ev.read = EventSourcePulse()
self.ev.write = EventSourcePulse()
self.ev.finalize()
self._connect_event(self.ev.read, self.ll.block_read_act,
self.ll.block_read_go)
self._connect_event(self.ev.write, self.ll.block_write_act,
self.ll.block_write_done)
# Wishbone access to SRAM buffers
self.bus = wishbone.Interface()
self.submodules.wb_rd_buffer = wishbone.SRAM(self.ll.rd_buffer,
read_only=False)
self.submodules.wb_wr_buffer = wishbone.SRAM(self.ll.wr_buffer,
read_only=False)
wb_slaves = [(lambda a: a[9] == 0, self.wb_rd_buffer.bus),
(lambda a: a[9] == 1, self.wb_wr_buffer.bus)]
self.submodules.wb_decoder = wishbone.Decoder(self.bus,
wb_slaves,
register=True)
# Local reset domain
self._reset = CSRStorage()
self.clock_domains.cd_local = ClockDomain()
self.comb += self.cd_local.clk.eq(ClockSignal())
self.comb += self.cd_local.rst.eq(ResetSignal() | self._reset.storage)
# Current data operation
self._read_act = CSRStatus()
self._read_addr = CSRStatus(32)
self._read_byteaddr = CSRStatus(32)
self._read_num = CSRStatus(32)
self._read_stop = CSRStatus()
self._write_act = CSRStatus()
self._write_addr = CSRStatus(32)
self._write_byteaddr = CSRStatus(32)
self._write_num = CSRStatus(32)
self._preerase_num = CSRStatus(23)
self._erase_start = CSRStatus(32)
self._erase_end = CSRStatus(32)
self.comb += [
self._read_act.status.eq(self.ll.block_read_act),
self._read_addr.status.eq(self.ll.block_read_addr),
self._read_byteaddr.status.eq(self.ll.block_read_byteaddr),
self._read_num.status.eq(self.ll.block_read_num),
self._read_stop.status.eq(self.ll.block_read_stop),
self._write_act.status.eq(self.ll.block_write_act),
self._write_addr.status.eq(self.ll.block_write_addr),
self._write_byteaddr.status.eq(self.ll.block_write_byteaddr),
self._write_num.status.eq(self.ll.block_write_num),
self._preerase_num.status.eq(self.ll.block_preerase_num),
self._erase_start.status.eq(self.ll.block_erase_start),
self._erase_end.status.eq(self.ll.block_erase_end),
]
# Informational registers, not needed for data transfer
self._info_bits = CSRStatus(16)
self.comb += self._info_bits.status.eq(
Cat(
self.ll.mode_4bit,
self.ll.mode_spi,
self.ll.host_hc_support,
Constant(False), # Reserved bit 3
Constant(False), # Reserved bit 4
Constant(False), # Reserved bit 5
Constant(False), # Reserved bit 6
Constant(False), # Reserved bit 7
self.ll.info_card_desel,
self.ll.err_op_out_range,
self.ll.err_unhandled_cmd,
self.ll.err_cmd_crc,
))
self._most_recent_cmd = CSRStatus(len(self.ll.cmd_in_cmd))
self.comb += self._most_recent_cmd.status.eq(self.ll.cmd_in_cmd)
self._card_status = CSRStatus(len(self.ll.card_status))
self.comb += self._card_status.status.eq(self.ll.card_status)
def __init__(self, platform):
csr_devices = []
self.submodules.crg = CRG(platform)
clk_freq = 125e6
self.submodules.rtm_magic = RTMMagic()
csr_devices.append("rtm_magic")
self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
csr_devices.append("rtm_identifier")
self.submodules.rtm_scratch = RTMScratch()
csr_devices.append("rtm_scratch")
# clock mux: 100MHz ext SMA clock to HMC830 input
self.submodules.clock_mux = gpio.GPIOOut(Cat(
platform.request("clk_src_ext_sel"),
platform.request("ref_clk_src_sel"),
platform.request("dac_clk_src_sel"),
platform.request("ref_lo_clk_sel")),
reset_out=0b0111)
csr_devices.append("clock_mux")
# Allaki: enable RF output, GPIO access to attenuator
self.comb += [
platform.request("allaki0_rfsw0").eq(1),
platform.request("allaki0_rfsw1").eq(1),
platform.request("allaki1_rfsw0").eq(1),
platform.request("allaki1_rfsw1").eq(1),
platform.request("allaki2_rfsw0").eq(1),
platform.request("allaki2_rfsw1").eq(1),
platform.request("allaki3_rfsw0").eq(1),
platform.request("allaki3_rfsw1").eq(1),
]
allaki_atts = [
platform.request("allaki0_att0"),
platform.request("allaki0_att1"),
platform.request("allaki1_att0"),
platform.request("allaki1_att1"),
platform.request("allaki2_att0"),
platform.request("allaki2_att1"),
platform.request("allaki3_att0"),
platform.request("allaki3_att1"),
]
allaki_att_gpio = []
for allaki_att in allaki_atts:
allaki_att_gpio += [
allaki_att.le,
allaki_att.sin,
allaki_att.clk,
allaki_att.rst_n,
]
self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio))
csr_devices.append("allaki_atts")
# HMC clock chip and DAC control
self.comb += platform.request("ad9154_rst_n").eq(1)
self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
csr_devices.append("converter_spi")
self.submodules.hmc7043_reset = gpio.GPIOOut(
platform.request("hmc7043_reset"), reset_out=1)
csr_devices.append("hmc7043_reset")
self.submodules.hmc7043_gpo = gpio.GPIOIn(
platform.request("hmc7043_gpo"))
csr_devices.append("hmc7043_gpo")
# DDMTD
self.clock_domains.cd_rtio = ClockDomain(reset_less=True)
rtio_clock_pads = platform.request("si5324_clkout_fabric")
self.specials += Instance("IBUFGDS", i_I=rtio_clock_pads.p, i_IB=rtio_clock_pads.n,
o_O=self.cd_rtio.clk)
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(
platform.request("rtm_master_aux_clk"), 150e6)
csr_devices.append("sysref_ddmtd")
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk, 8.)
serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += [
self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),
self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset)
]
csr_devices.append("serwb_phy_rtm")
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master")
self.submodules += serwb_core
# process CSR devices and connect them to serwb
self.csr_regions = []
wb_slaves = WishboneSlaveManager(0x10000000)
for i, name in enumerate(csr_devices):
origin = i*CSR_RANGE_SIZE
module = getattr(self, name)
csrs = module.get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
self.csr_regions.append((name, origin, 32, csrs))
self.submodules += wishbone.Decoder(serwb_core.etherbone.wishbone.bus,
wb_slaves.get_interconnect_slaves(),
register=True)
def __init__(self, platform):
csr_devices = []
self.submodules.crg = CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
clk_freq = 125e6
platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
self.submodules.rtm_identifier = RTMIdentifier()
csr_devices.append("rtm_identifier")
# clock mux: 125MHz ext SMA clock to HMC830 input
self.comb += [
platform.request("clk_src_ext_sel").eq(1), # use ext clk from sma
platform.request("ref_clk_src_sel").eq(1),
platform.request("dac_clk_src_sel").eq(0), # use clk from dac_clk
]
self.comb += [
platform.request("ad9154_rst_n").eq(1),
platform.request("ad9154_txen", 0).eq(0b11),
platform.request("ad9154_txen", 1).eq(0b11)
]
self.submodules.converter_spi = spi.SPIMaster([
platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)])
csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0)
# AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1)
self.submodules += serwb_pll
serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave")
self.submodules.serwb_phy = serwb_phy
self.comb += self.crg.reset.eq(serwb_phy.init.reset)
serwb_phy.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes.clk, 32.0),
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes_20x.clk, 1.6),
platform.add_period_constraint(serwb_phy.serdes.cd_serwb_serdes_5x.clk, 6.4)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
serwb_phy.serdes.cd_serwb_serdes.clk,
serwb_phy.serdes.cd_serwb_serdes_5x.clk)
serwb_core = serwb.core.SERWBCore(serwb_phy, int(clk_freq), mode="master")
self.submodules += serwb_core
# process CSR devices and connect them to serwb
self.csr_regions = []
wb_slaves = WishboneSlaveManager(0x10000000)
for i, name in enumerate(csr_devices):
origin = i*CSR_RANGE_SIZE
module = getattr(self, name)
csrs = module.get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
self.csr_regions.append((name, origin, 32, csrs))
self.submodules += wishbone.Decoder(serwb_core.etherbone.wishbone.bus,
wb_slaves.get_interconnect_slaves(),
register=True)
