def __init__(self, platform, **kwargs): SDRAMSoC.__init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000000, cpu_reset_address=0x00180000, **kwargs) sdram_geom = lasmicon.GeomSettings( bank_a=2, row_a=13, col_a=10 ) sdram_timing = lasmicon.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(15), tWTR=2, tREFI=self.ns(7800, False), tRFC=self.ns(70), req_queue_size=8, read_time=32, write_time=16 ) self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing) # Wishbone self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"), self.ns(110), self.ns(50)) self.flash_boot_address = 0x001a0000 self.register_rom(self.norflash.bus) self.submodules.minimac = minimac3.MiniMAC(platform.request("eth")) self.add_wb_slave(lambda a: a[26:29] == 3, self.minimac.membus) self.add_cpu_memory_region("minimac_mem", 0xb0000000, 0x1800) # CSR self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) if platform.name == "mixxeo": self.submodules.leds = gpio.GPIOOut(platform.request("user_led")) if platform.name == "m1": self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2))) self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2))) # Clock glue self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb) ] platform.add_platform_command(""" INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE; """) # add Verilog sources for d in ["mxcrg", "minimac3"]: platform.add_source_dir(os.path.join("verilog", d))
def __init__(self, platform, **kwargs): clk_freq = 80*1000*1000 SDRAMSoC.__init__(self, platform, clk_freq, cpu_reset_address=0x60000, **kwargs) self.submodules.crg = _CRG(platform, clk_freq) sdram_geom = lasmicon.GeomSettings( bank_a=2, row_a=12, col_a=8 ) sdram_timing = lasmicon.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(14), tWTR=2, tREFI=self.ns(64*1000*1000/4096, False), tRFC=self.ns(66), req_queue_size=8, read_time=32, write_time=16 ) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing) # BIOS is in SPI flash self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), cmd=0xefef, cmd_width=16, addr_width=24, dummy=4, div=6) self.flash_boot_address = 0x70000 self.register_rom(self.spiflash.bus)
def __init__(self, platform, **kwargs): SDRAMSoC.__init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000000, cpu_reset_address=0x00180000, **kwargs) sdram_geom = lasmicon.GeomSettings( bank_a=2, row_a=13, col_a=10 ) sdram_timing = lasmicon.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(15), tWTR=2, tREFI=self.ns(7800, False), tRFC=self.ns(70), req_queue_size=8, read_time=32, write_time=16 ) self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing) self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"), self.ns(110), self.ns(50)) self.flash_boot_address = 0x001a0000 self.register_rom(self.norflash.bus) self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) self.comb += [ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb) ] platform.add_platform_command(""" INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE; """) platform.add_source_dir(os.path.join("verilog", "mxcrg"))
def __init__(self, platform, **kwargs): SDRAMSoC.__init__(self, platform, clk_freq=125*1000000, cpu_reset_address=0xaf0000, **kwargs) self.submodules.crg = _CRG(platform) sdram_geom = lasmicon.GeomSettings( bank_a=3, row_a=16, col_a=10 ) sdram_timing = lasmicon.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(15), tWTR=2, tREFI=self.ns(7800, False), tRFC=self.ns(70), req_queue_size=8, read_time=32, write_time=16 ) self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3") self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing) # BIOS is in SPI flash spiflash_pads = platform.request("spiflash") spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, cmd=0xfffefeff, cmd_width=32, addr_width=24, dummy=11, div=2) self.flash_boot_address = 0xb00000 self.register_rom(self.spiflash.bus)
def __init__(self, platform, **kwargs): clk_freq = int(80e6) SDRAMSoC.__init__(self, platform, clk_freq=clk_freq, cpu_reset_address=0x160000, sram_size=0x400, **kwargs) platform.add_extension(_ventilator_io) platform.ise_commands = """ trce -v 12 -fastpaths -o {build_name} {build_name}.ncd {build_name}.pcf """ self.submodules.crg = _CRG(platform, clk_freq) sdram_geom = lasmicon.GeomSettings( bank_a=2, row_a=12, col_a=8 ) sdram_timing = lasmicon.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(14), tWTR=2, tREFI=self.ns(64e6/4096, False), tRFC=self.ns(66), req_queue_size=8, read_time=32, write_time=16 ) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing) # BIOS is in SPI flash self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), cmd=0xefef, cmd_width=16, addr_width=24, dummy=4, div=4) self.flash_boot_address = 0x70000 self.register_rom(self.spiflash.bus) self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2))) #self.comb += platform.request("user_led", 0).eq(ResetSignal()) if False: self.submodules.test_inputs = gpio.GPIOIn(platform.request("inputs")) self.submodules.test_ttl = ttlgpio.TTLGPIO(platform.request("ttl")) self.submodules.dds = ad9858.AD9858(platform.request("dds")) self.add_wb_slave( lambda a: (a & (0x70000000 >> 2)) == (0x30000000 >> 2), self.dds.bus) else: #self.submodules.gp = ventilator.Gpio(platform.request("all_gpio")) # have ise distribute the two pll signals and the bufplls to # banks 0 and 1. gpio distribution on the banks is: # 4 in, 8 out, 4 out on bank0 and 4out, 2oe on bank1 self.submodules.gp = ventilator.HiresGpio(platform.request("all_gpio"), cdmap=[0] * (4 + 8 + 4) + [1] * (4 + 2)) self.comb += self.gp.sys8_stb.eq(self.crg.sys8_stb) self.submodules.wb = ventilator.Wishbone() self.submodules.dds = ad9858.AD9858(platform.request("dds")) self.submodules.ventilator = ventilator.Master([ (self.gp, 0x00000100, 0xffffff00), #(self.dds, 0x00010000, 0xffff0000), (self.wb, 0x20000000, 0xe0000000), # 0bxxxWSSSS #(self.spi, 0x40000000, 0xe0000000), #(self.i2c, 0x60000000, 0xe0000000), ]) self.submodules.wbcon = wishbone.Decoder(self.wb.bus, [ (lambda a: (a & 0x00ffff00) == 0x00000000, self.dds.bus), ]) self.add_wb_slave( lambda a: (a & (0x70000000 >> 2)) == (0x30000000 >> 2), self.ventilator.bus)