Remark:
"""
DESIGN_NAME = 'test_bg_bf_db'
NOF_INPUTS = 6
#C_BF = {'nof_signal_paths' : 8,
# 'nof_input_streams' : NOF_INPUTS,
# 'nof_subbands' : 16,
# 'nof_weights' : 64,
# 'in_dat_w' : 16,
# 'in_weight_w' : 16,
# 'bst_gain_w' : 1,
# 'bst_dat_w' : 16,
# 'out_gain_w' : -5,
# 'out_dat_w' : 8,
# 'stat_data_w' : 56,
# 'stat_data_sz' : 2 }
#
C_BF = (64, 16, 24, 256, 4, 16, 16, 0, 16, -6, 8, 56, 2)
bg = mms_diag_block_gen(g_nof_streams = 'NOF_INPUTS', g_nof_errors = 4) # Generates 8 beamlet streams
bf = bf_unit(g_bf=C_BF) # Beam forms 12 telescope input streams into one output stream
db = mms_diag_data_buffer(g_nof_streams=1) # Offload: UDP packetizes the BF output stream
ct = ctrl_unb1_board() # Contains our Ethernet core that puts the UDP packets on the line
#connections = bg>bf>ol>ct # Connect the components
mm = mm_master("mmm_bg_bf_db", [bg,bf,db,ct]) # Instantiate the MM controller
top = Entity(DESIGN_NAME, [bg,bf,db,ct,mm], info=INFO) # Declare our top level, pass its subcomponents and their connections
top.architecture.generate() # Generate the VHDL
from mms_diag_block_gen import mms_diag_block_gen from bf_unit import bf_unit from ctrl_unb2_board import ctrl_unb2_board from mm_master import mm_master INFO = """ Purpose: . Beam form and UDP packetize generated data (emulates 12 telescope outputs) Description . A block generator emulates incoming data from 1 polarization, 12 telescopes. . 12 streams in parallel . Each polarisation substream contains 704 beamlet samples per time sample. . For each polarization Remark: . This precedes a dual-pol design that uses two BF units -> dp_mux. """ DESIGN_NAME = 'arts_unb2_sc1_bg_single_pol' NOF_TELESCOPES = 12 bg = mms_diag_block_gen(NOF_TELESCOPES) # Generates 12 beamlet streams bf = bf_unit(NOF_TELESCOPES) # Beam forms 12 telescope input streams into one output stream ol = arts_sc1_offload() # Offload: UDP packetizes the BF output stream ct = ctrl_unb2_board() # Contains our Ethernet core that puts the UDP packets on the line #connections = bg>bf>ol>ct # Connect the components mm = mm_master([bg,bf,ol,ct]) # Instantiate the MM controller top = Component(DESIGN_NAME, [bg,bf,ol,ct,mm], info=INFO) # Declare our top level, pass its subcomponents and their connections top.generate() # Generate the VHDL
