def __init__(self):
platform = nexys4ddr.Platform()
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="picorv32",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(16)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(16)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*
[platform.request("btn%c" % c) for c in ['c', 'd', 'u', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# RGB leds
SoCCore.add_csr(self, "led16")
self.submodules.led16 = rgbled.RGBLed(platform.request("led", 16))
SoCCore.add_csr(self, "led17")
self.submodules.led17 = rgbled.RGBLed(platform.request("led", 17))
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# Joystick SPI
SoCCore.add_csr(self, "joystick")
self.submodules.joystick = spijoystick.SpiJoystick(
platform.request("joystick"))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
def __init__(self):
platform = tarjeta.Platform()
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x6000,
integrated_main_ram_size=2 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
SoCCore.add_csr(self, "ledRGB_1")
self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1))
SoCCore.add_csr(self, "ledRGB_2")
self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
def __init__(self):
platform = tarjeta.Platform()
## add source verilog
platform.add_source("module/verilog/camara.v")
platform.add_source("module/verilog/Infrarrojo/modulo_ir.v")
platform.add_source("module/verilog/PWM/BloquePWM.v")
platform.add_source("module/verilog/PWM/PWM.v")
platform.add_source("module/verilog/PWM/MaquinaEstadosPWM.v")
platform.add_source("module/verilog/PWM/DivFreqPWM.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/bloqueultrasonido.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/contador.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/divisor.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrec.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecd.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecgen.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecme.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/genpulsos.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/maquinadeestados.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/meultrasonido.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/ultrasonido.v")
clk_freq = 100e6
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
SoCCore.add_csr(self, "ledRGB_1")
self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1))
SoCCore.add_csr(self, "ledRGB_2")
self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
#camara
"""
/* SoCCore.add_csr(self,"camara_cntrl")
SoCCore.add_interrupt(self,"camara_cntrl")
cam_data_in = Cat(*[platform.request("cam_data_in", i) for i in range(8)])
self.submodules.camara_cntrl = camara.Camara(platform.request("cam_xclk"),platform.request("cam_pclk"),cam_data_in)
"""
#serialA
from litex.soc.cores import uart
self.submodules.uart1_phy = uart.UARTPHY(
pads=platform.request("uart1"),
clk_freq=self.sys_clk_freq,
baudrate=9600)
self.submodules.uart1 = ResetInserter()(uart.UART(self.uart1_phy,
tx_fifo_depth=16,
rx_fifo_depth=16))
self.csr.add("uart1_phy", use_loc_if_exists=True)
self.csr.add("uart1", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"):
self.irq.add("uart1", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")
#Infrarrojo
SoCCore.add_csr(self, "infrarrojo_cntrl")
self.submodules.infrarrojo_cntrl = infrarrojo.Infrarrojo(
platform.request("ir_inout"))
#PWM
SoCCore.add_csr(self, "pwm_cntrl")
self.submodules.pwm_cntrl = pwm.PWM(platform.request("pwm_out"))
#Ultrasonido
SoCCore.add_csr(self, "ultrasonido")
self.submodules.ultrasonido = ultrasonido.Ultrasonido(
platform.request("us_trigger"), platform.request("us_echo"))
def __init__(self):
platform = tarjeta.Platform()
## add source verilog
# camara.v
platform.add_source("module/verilog/camara/camara.v")
platform.add_source("module/verilog/camara/buffer_ram_dp.v")
platform.add_source("module/verilog/camara/cam_read.v")
platform.add_source("module/verilog/camara/procesamiento.v")
platform.add_source("module/verilog/camara/VGA_driver.v")
platform.add_source("module/verilog/camara/PLL/clk24_25_nexys4.v")
platform.add_source("module/verilog/camara/PLL/clk24_25_nexys4_0.v")
platform.add_source(
"module/verilog/camara/PLL/clk24_25_nexys4_clk_wiz.v")
# Radar
platform.add_source("module/verilog/radar/radar.v")
platform.add_source("module/verilog/radar/servo.v")
platform.add_source("module/verilog/radar/ultrasonido1.v")
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=10 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
#SoCCore.add_csr(self,"ledRGB_1")
#self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB",1))
#SoCCore.add_csr(self,"ledRGB_2")
#self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB",2))
# VGA
#SoCCore.add_csr(self,"vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i)
for i in range(4)]) # Se concatena
vsync = platform.request("vsync")
hsync = platform.request("hsync")
#self.submodules.vga_cntrl = vgacontroller.VGAcontroller(hsync,vsync, vga_red, vga_green, vga_blue)
#camara
SoCCore.add_csr(self, "camara_cntrl") # Incluir mapa de memoria
SoCCore.add_interrupt(self, "camara_cntrl")
cam_data_in = Cat(
*[platform.request("cam_data_in", i) for i in range(8)])
self.submodules.camara_cntrl = camara.Camara(
vsync, hsync, vga_red, vga_green, vga_blue,
platform.request("cam_xclk"), platform.request("cam_pwdn"),
platform.request("cam_pclk"), cam_data_in,
platform.request("cam_vsync"), platform.request("cam_href"))
# radar
SoCCore.add_csr(self, "radar_cntrl") # Incluir mapa de memoria
self.submodules.radar_cntrl = radar.Radar(platform.request("echo"),
platform.request("done"),
platform.request("trigger"),
platform.request("PWM"))
def __init__(self):
platform = tarjeta.Platform()
## add source verilog
platform.add_source("module/verilog/camara.v")
clk_freq = 100e6
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
SoCCore.add_csr(self, "ledRGB_1")
self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1))
SoCCore.add_csr(self, "ledRGB_2")
self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
#camara
SoCCore.add_csr(self, "camara_cntrl")
SoCCore.add_interrupt(self, "camara_cntrl")
cam_data_in = Cat(
*[platform.request("cam_data_in", i) for i in range(8)])
self.submodules.camara_cntrl = camara.Camara(
platform.request("cam_xclk"), platform.request("cam_pclk"),
cam_data_in)
#serialA
from litex.soc.cores import uart
self.submodules.uart1_phy = uart.UARTPHY(
pads=platform.request("uart1"),
clk_freq=self.sys_clk_freq,
baudrate=115200)
self.submodules.uart1 = ResetInserter()(uart.UART(self.uart1_phy,
tx_fifo_depth=16,
rx_fifo_depth=16))
self.csr.add("uart1_phy", use_loc_if_exists=True)
self.csr.add("uart1", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"):
self.irq.add("uart1", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")