def main():
model = MixedSignalModel('model')
model.add_analog_input('a')
model.add_analog_input('b')
model.bind_name('c', model.a + model.b)
model.compile_and_print(VerilogGenerator())
def main():
tau = 1e-6
dt = 0.1e-6
model = MixedSignalModel('model', dt=dt)
model.add_analog_input('v_in')
model.add_analog_output('v_out', init=1.23)
model.add_eqn_sys([Deriv(model.v_out) == (model.v_in - model.v_out)/tau])
model.compile_and_print(VerilogGenerator())
def main():
dt = 0.1e-6
m = MixedSignalModel('model', dt=dt)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_eqn_sys([m.v_out == 0.123 * m.v_in])
m.compile_and_print(VerilogGenerator())
def main():
model = MixedSignalModel('model')
model.add_analog_input('a')
model.add_digital_input('b', width=8)
model.add_digital_output('c', width=12)
model.bind_name('d', model.a + model.b)
clamped = clamp(to_sint(model.d, width=model.c.width + 1), 0, 1023)
model.set_next_cycle(model.c, to_uint(clamped, width=model.c.width))
model.compile_and_print(VerilogGenerator())
def main():
dt = 0.1e-6
num = (1e12,)
den = (1, 8e5, 1e12,)
model = MixedSignalModel('model', dt=dt)
model.add_analog_input('v_in')
model.add_analog_output('v_out')
model.set_tf(input_=model.v_in, output=model.v_out, tf=(num, den))
model.compile_and_print(VerilogGenerator())
def main():
# define ports
m = MixedSignalModel('comparator')
m.add_analog_input('in_p')
m.add_analog_input('in_n')
m.add_digital_output('out', init=0)
m.add_digital_input('clk')
# define behavior
m.immediate_assign('out_async', m.in_p > m.in_n)
m.next_cycle_assign(m.out, m.out_async, clk=m.clk)
# write model
m.compile_and_print(VerilogGenerator())
def main():
tau = 1e-6
dt = 0.1e-6
model = MixedSignalModel('model', dt=dt)
model.add_analog_input('v_in')
model.add_analog_output('v_out')
model.add_digital_input('ctrl')
model.add_eqn_sys([
Deriv(
model.v_out) == eqn_case([0, 1 / tau], [model.ctrl]) * model.v_in -
model.v_out / tau
])
model.compile_and_print(VerilogGenerator())
def main():
tau_det_fast = 1e-9
tau_det_slow = 360e-9
dt = 4.6e-9
m = MixedSignalModel('model', dt=dt)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.bind_name('in_gt_out', m.v_in > m.v_out)
# detector dynamics
m.add_eqn_sys([
Deriv(m.v_out) == eqn_case([0, 1 / tau_det_fast], [m.in_gt_out]) * (m.v_in - m.v_out) - (m.v_out / tau_det_slow)
])
m.compile_and_print(VerilogGenerator())
def main():
dt = 0.1e-6
res = 1e3
cap = 1e-9
m = MixedSignalModel('model', dt=dt)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
c = m.make_circuit()
gnd = c.make_ground()
c.capacitor('net_v_out', gnd, cap, voltage_range=RangeOf(m.v_out))
c.resistor('net_v_in', 'net_v_out', res)
c.voltage('net_v_in', gnd, m.v_in)
c.add_eqns(AnalogSignal('net_v_out') == m.v_out)
m.compile_and_print(VerilogGenerator())
def main():
model = MixedSignalModel('model')
model.add_analog_input('a_in')
model.add_digital_output('d_out', width=8)
model.add_analog_output('a_out')
model.add_digital_input('d_in', width=8)
# DAC from 0 to 1V as the input code varies from 0-255
clamped = clamp(to_sint(model.a_in * 255, width=model.d_out.width + 1), 0,
255)
model.set_this_cycle(model.d_out, to_uint(clamped,
width=model.d_out.width))
# ADC code goes from 0-255 as input voltage goes from 0 to 1V
model.set_this_cycle(model.a_out, model.d_in / 255)
model.compile_and_print(VerilogGenerator())
def main():
dt = 0.1e-6
m = MixedSignalModel('model', dt=dt)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('sw1')
m.add_digital_input('sw2')
c = m.make_circuit()
gnd = c.make_ground()
c.voltage('net_v_in', gnd, m.v_in)
c.switch('net_v_in', 'net_v_x', m.sw1, r_on=1.0, r_off=2.0)
c.switch('net_v_x', gnd, m.sw2, r_on=3.0, r_off=4.0)
c.add_eqns(
AnalogSignal('net_v_x') == m.v_out
)
m.compile_and_print(VerilogGenerator())
def main():
dt = 0.01e-6
cap = 0.16e-6
ind = 0.16e-6
res = 0.1
model = MixedSignalModel('model', dt=dt)
model.add_analog_input('v_in')
model.add_analog_output('v_out')
model.add_analog_state('i_ind', 100)
v_l = AnalogSignal('v_l')
v_r = AnalogSignal('v_r')
eqns = [
Deriv(model.i_ind) == v_l / ind,
Deriv(model.v_out) == model.i_ind / cap, v_r == model.i_ind * res,
model.v_in == model.v_out + v_l + v_r
]
model.add_eqn_sys(eqns)
model.compile_and_print(VerilogGenerator())
def main():
dt = 1e-9
m = MixedSignalModel('model', dt=dt)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('sw1')
m.add_digital_input('sw2')
c = m.make_circuit()
gnd = c.make_ground()
c.voltage('net_v_in', gnd, m.v_in)
c.switch('net_v_in', 'net_v_x', m.sw1)
c.switch('net_v_x', gnd, m.sw2)
c.inductor('net_v_in', 'net_v_x', 1, current_range=100)
c.add_eqns(AnalogSignal('net_v_x') == m.v_out)
m.compile_and_print(VerilogGenerator())
