def _convertGens(genlist, vfile):
blockBuf = StringIO()
funcBuf = StringIO()
for tree in genlist:
if isinstance(tree, _UserVerilogCode):
blockBuf.write(str(tree))
continue
if tree.kind == _kind.ALWAYS:
Visitor = _ConvertAlwaysVisitor
elif tree.kind == _kind.INITIAL:
Visitor = _ConvertInitialVisitor
elif tree.kind == _kind.SIMPLE_ALWAYS_COMB:
Visitor = _ConvertSimpleAlwaysCombVisitor
elif tree.kind == _kind.ALWAYS_DECO:
Visitor = _ConvertAlwaysDecoVisitor
elif tree.kind == _kind.ALWAYS_SEQ:
Visitor = _ConvertAlwaysSeqVisitor
else: # ALWAYS_COMB
Visitor = _ConvertAlwaysCombVisitor
v = Visitor(tree, blockBuf, funcBuf)
v.visit(tree)
vfile.write(funcBuf.getvalue())
funcBuf.close()
vfile.write(blockBuf.getvalue())
blockBuf.close()
def _convertGens(genlist, vfile):
blockBuf = StringIO()
funcBuf = StringIO()
for tree in genlist:
if isinstance(tree, _UserVerilogCode):
blockBuf.write(str(tree))
continue
if tree.kind == _kind.ALWAYS:
Visitor = _ConvertAlwaysVisitor
elif tree.kind == _kind.INITIAL:
Visitor = _ConvertInitialVisitor
elif tree.kind == _kind.SIMPLE_ALWAYS_COMB:
Visitor = _ConvertSimpleAlwaysCombVisitor
elif tree.kind == _kind.ALWAYS_DECO:
Visitor = _ConvertAlwaysDecoVisitor
elif tree.kind == _kind.ALWAYS_SEQ:
Visitor = _ConvertAlwaysSeqVisitor
else: # ALWAYS_COMB
Visitor = _ConvertAlwaysCombVisitor
v = Visitor(tree, blockBuf, funcBuf)
v.visit(tree)
vfile.write(funcBuf.getvalue())
funcBuf.close()
vfile.write(blockBuf.getvalue())
blockBuf.close()
def _writeModuleHeader(f, intf, doc):
print("module %s (" % intf.name, file=f)
b = StringIO()
for portname in intf.argnames:
print(" %s," % portname, file=b)
print(b.getvalue()[:-2], file=f)
b.close()
print(");", file=f)
print(doc, file=f)
print(file=f)
for portname in intf.argnames:
s = intf.argdict[portname]
if s._name is None:
raise ToVerilogError(_error.ShadowingSignal, portname)
if s._inList:
raise ToVerilogError(_error.PortInList, portname)
# make sure signal name is equal to its port name
s._name = portname
r = _getRangeString(s)
p = _getSignString(s)
if s._driven:
if s._read:
warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
category=ToVerilogWarning)
print("output %s%s%s;" % (p, r, portname), file=f)
if s._driven == 'reg':
print("reg %s%s%s;" % (p, r, portname), file=f)
else:
print("wire %s%s%s;" % (p, r, portname), file=f)
else:
if not s._read:
warnings.warn("%s: %s" % (_error.UnusedPort, portname),
category=ToVerilogWarning)
print("input %s%s%s;" % (p, r, portname), file=f)
print(file=f)
def _writeTestBench(f, intf, trace=False):
print("module tb_%s;" % intf.name, file=f)
print(file=f)
fr = StringIO()
to = StringIO()
pm = StringIO()
for portname in intf.argnames:
s = intf.argdict[portname]
r = _getRangeString(s)
if s._driven:
print("wire %s%s;" % (r, portname), file=f)
print(" %s," % portname, file=to)
else:
print("reg %s%s;" % (r, portname), file=f)
print(" %s," % portname, file=fr)
print(" %s," % portname, file=pm)
print(file=f)
print("initial begin", file=f)
if trace:
print(' $dumpfile("%s.vcd");' % intf.name, file=f)
print(' $dumpvars(0, dut);', file=f)
if fr.getvalue():
print(" $from_myhdl(", file=f)
print(fr.getvalue()[:-2], file=f)
print(" );", file=f)
if to.getvalue():
print(" $to_myhdl(", file=f)
print(to.getvalue()[:-2], file=f)
print(" );", file=f)
print("end", file=f)
print(file=f)
print("%s dut(" % intf.name, file=f)
print(pm.getvalue()[:-2], file=f)
print(");", file=f)
print(file=f)
print("endmodule", file=f)
def _writeTestBench(f, intf, trace=False):
print("module tb_%s;" % intf.name, file=f)
print(file=f)
fr = StringIO()
to = StringIO()
pm = StringIO()
for portname in intf.argnames:
s = intf.argdict[portname]
r = _getRangeString(s)
if s._driven:
print("wire %s%s;" % (r, portname), file=f)
print(" %s," % portname, file=to)
else:
print("reg %s%s;" % (r, portname), file=f)
print(" %s," % portname, file=fr)
print(" %s," % portname, file=pm)
print(file=f)
print("initial begin", file=f)
if trace:
print(' $dumpfile("%s.vcd");' % intf.name, file=f)
print(' $dumpvars(0, dut);', file=f)
if fr.getvalue():
print(" $from_myhdl(", file=f)
print(fr.getvalue()[:-2], file=f)
print(" );", file=f)
if to.getvalue():
print(" $to_myhdl(", file=f)
print(to.getvalue()[:-2], file=f)
print(" );", file=f)
print("end", file=f)
print(file=f)
print("%s dut(" % intf.name, file=f)
print(pm.getvalue()[:-2], file=f)
print(");", file=f)
print(file=f)
print("endmodule", file=f)
def _writeModuleHeader(f, intf, doc):
print("module %s (" % intf.name, file=f)
b = StringIO()
for portname in intf.argnames:
print(" %s," % portname, file=b)
print(b.getvalue()[:-2], file=f)
b.close()
print(");", file=f)
print(doc, file=f)
print(file=f)
for portname in intf.argnames:
s = intf.argdict[portname]
if s._name is None:
raise ToVerilogError(_error.ShadowingSignal, portname)
if s._inList:
raise ToVerilogError(_error.PortInList, portname)
# make sure signal name is equal to its port name
s._name = portname
r = _getRangeString(s)
p = _getSignString(s)
if s._driven:
if s._read :
if not isinstance(s, _TristateSignal):
warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
category=ToVerilogWarning
)
if isinstance(s, _TristateSignal):
print("inout %s%s%s;" % (p, r, portname), file=f)
else:
print("output %s%s%s;" % (p, r, portname), file=f)
if s._driven == 'reg':
print("reg %s%s%s;" % (p, r, portname), file=f)
else:
print("wire %s%s%s;" % (p, r, portname), file=f)
else:
if not s._read:
warnings.warn("%s: %s" % (_error.UnusedPort, portname),
category=ToVerilogWarning
)
print("input %s%s%s;" % (p, r, portname), file=f)
print(file=f)