def run(self, clks):
"""
Run a test bench simulation.
"""
myhdlvpi = os.path.join(config.verilogdir, 'myhdl.vpi')
command = "vvp -m {myhdlvpi} {executable}".format(myhdlvpi=myhdlvpi, executable=self.executable)
cosimdict = dict([(sn, getattr(self, sn)) for sn in self.signal_names])
dut = Cosimulation(command, **cosimdict)
drivers = [df() for df in self.drivers]
sim = Simulation(dut, *drivers)
sim.run(2*clks)
dut.__del__()
del dut
def run(self, clks):
"""
Run a test bench simulation.
"""
myhdlvpi = os.path.join(config.verilogdir, 'myhdl.vpi')
command = "vvp -m {myhdlvpi} {executable}".format(
myhdlvpi=myhdlvpi, executable=self.executable)
cosimdict = dict([(sn, getattr(self, sn)) for sn in self.signal_names])
dut = Cosimulation(command, **cosimdict)
drivers = [df() for df in self.drivers]
sim = Simulation(dut, *drivers)
sim.run(2 * clks)
dut.__del__()
del dut
def NeuronBlock(ports, params):
os.system(
cmd %
(params.leak_width, params.weight_width, params.threshold_width,
params.potential_width, params.num_weights, params.num_reset_modes))
return Cosimulation("vvp -m ../iverilog/myhdl.vpi NeuronBlock.o",
**ports._asdict())
def bin2gray(B, G):
width = len(B)
os.system(cmd % width)
# return Cosimulation("C:/iverilog/bin/vvp.exe -M -m myhdl bin2gray.o", B=B, G=G)
# print(os.path)
# os.system("vvp -M ./ -m myhdl bin2gray") C:/Users/sanmu/PycharmProjects/TestMyHDL
return Cosimulation("vvp -m .\myhdl64.vpi bin2gray.o", B=B, G=G)
def _cosim(self):
self._prepare_cosim()
cmd = self.__sim.get_run_cmd(self.__wrapper, lib=self.__worklib)
cosim_kwargs = {k: v[0] for k, v in self.__port.items()}
logging.debug('[%s] Cosim kwargs: %s', self, cosim_kwargs)
cosim = Cosimulation(cmd, **cosim_kwargs)
return cosim
def ForwardEastWest(ports, params):
os.system(cmd %
(params.packet_width, params.dx_msb, params.dx_lsb,
params.dy_msb, params.dy_lsb, params.buffer_depth, params.east))
return Cosimulation("vvp -m ../iverilog/myhdl.vpi ./ForwardEastWest.o",
**ports._asdict())
def bin2gray(B, G, width):
os.system('vlog -quiet +define+width=%s ../../test/verilog/bin2gray.v' %
(width))
os.system(
'vlog -quiet +define+width=%s ../../test/verilog/dut_bin2gray.v' %
(width))
return Cosimulation(cmd, B=B, G=G)
def bin2grayCoSim(B, G, DATA = 8):
bin2gray_inst = bin2gray(B, G, DATA = DATA)
name='bin2gray_' + str(DATA)
bin2gray_inst.convert(hdl='Verilog', header=hdlcfg.header, name=name)
os.system("iverilog -o bin2gray.o " + \
"{0}.v ".format(name) + \
"{0}.v ".format('tb_' + name))
return Cosimulation("vvp -m myhdl bin2gray.o", B=B, G=G)
def v_im(clock, pc, dout, infile):
cmd = 'iverilog -o %s %s %s -Din_file=%s' % (
IM_cosim_o, IM_cosim_v, IM_v, "../samples/Index_Memory_256.hex")
os.system(cmd)
return Cosimulation("vvp -m %s %s" % (myhdl_vpi, IM_cosim_o),
clock=clock,
addr=pc,
Instr=dout)
def fir(clk, resetn, enable, inP, outP, out_enable):
os.system(cmd)
return Cosimulation("vvp -m ./myhdl fir.o -fst",
clk=clk,
resetn=resetn,
enable=enable,
inP=inP,
outP=outP,
out_enable=out_enable)
def v_dm(clock, MR, MW, Addr, WD, RD):
cmd = 'iverilog -o %s %s %s' % (DM_cosim_o, DM_cosim_v, DM_v)
os.system(cmd)
return Cosimulation("vvp -m %s %s" % (myhdl_vpi, DM_cosim_o),
Clk=clock,
MR=MR,
MW=MW,
Addr=Addr,
WD=WD,
RD=RD)
def buffer(clk, rst, din, din_valid, read_en, dout, empty, full, depth=4):
os.system(cmd % (len(din), depth))
return Cosimulation('vvp -m ../iverilog/myhdl.vpi buffer.o',
clk=clk,
rst=rst,
din=din,
din_valid=din_valid,
read_en=read_en,
dout=dout,
empty=empty,
full=full)
def v_alu(clock, reset, ALUcontrol, A, B, R, zero):
cmd = "iverilog -o %s %s %s" % (ALU_cosim_o, ALU_cosim_v, ALU_v)
os.system(cmd)
return Cosimulation("vvp -m %s %s" % (myhdl_vpi, ALU_cosim_o),
clock=clock,
reset=reset,
ALUcontrol=ALUcontrol,
A=A,
B=B,
R=R,
zero=zero)
def bin2grayCoSim(B, G, DATA=8):
functionStat(inspect.currentframe().f_code.co_name, __name__)
bin2gray_inst = bin2gray(B, G, DATA=DATA)
name = 'bin2gray_' + str(DATA)
bin2gray_inst.convert(hdl='Verilog',
header=hdlcfg.header,
directory=hdlcfg.hdl_path,
name=name)
os.system("iverilog -o bin2gray.o " + \
hdlcfg.hdl_path+"/{0}.v ".format(name) + \
hdlcfg.hdl_path+"/{0}.v ".format('tb_' + name))
return Cosimulation("vvp -m myhdl bin2gray.o -vcd test.vcd", B=B, G=G)
def setupCosimulationIcarus(options, parameters, kwargs, \ srcprefix = "", tbprefix = None): try: libfiles = options['libfiles'] except KeyError: libfiles = "" if not tbprefix: tbprefix = srcprefix name = options['name'] if 'tbname' in options: tbname = options['tbname'] else: tbname = name objfile = "%s.o" % name if os.path.exists(objfile): os.remove(objfile) analyze_cmd = ['iverilog' ] analyze_cmd += ['-s', "tb_" + tbname] analyze_cmd += ['-D', "mixed_hdl"] src = srcprefix + '%s.v' % name tbsrc = tbprefix + 'tb_%s.v' % tbname for p in parameters.keys(): analyze_cmd += [ '-P', 'tb_%s.%s=%s' % (tbname, p, parameters[p]) ] analyze_cmd += ['-o', objfile, src, tbsrc] analyze_cmd += libfiles print(analyze_cmd) subprocess.call(analyze_cmd) simulate_cmd = ['vvp', '-m', MYHDL_COSIMULATION + '/myhdl.vpi'] simulate_cmd += IVL_MODULE_PATH_ARGS simulate_cmd += [objfile] c = Cosimulation(simulate_cmd, **kwargs) c.name = name return c
def setupCosimulationIcarus(**kwargs):
name = kwargs['name']
objfile = "%s.o" % name
if path.exists(objfile):
os.remove(objfile)
analyze_cmd = ['iverilog', '-o', objfile, '%s.v' % name, 'tb_%s.v' % name]
subprocess.call(analyze_cmd)
if sys.platform != "win32":
simulate_cmd = [
'vvp', '-m', '../../../../cosimulation/icarus/myhdl.vpi', objfile
]
else:
# assume that myhdl.vpi has been copied to the iverilog\lib\ivl
simulate_cmd = ['vvp', '-m', 'myhdl', objfile]
return Cosimulation(simulate_cmd, **kwargs)
def RANCNetwork(input_ports, output_ports, params):
os.system(
cmd %
(params.grid_dimension_x, params.grid_dimension_y,
params.output_core_x_coordinate, params.output_core_y_coordinate,
params.num_outputs, params.num_neurons, params.num_axons,
params.num_ticks, params.num_weights, params.num_reset_modes,
params.potential_width, params.weight_width, params.leak_width,
params.threshold_width, params.dx_msb, params.dx_lsb, params.dy_msb,
params.dy_lsb, params.input_buffer_depth, params.router_buffer_depth,
params.memory_filepath, params.maximum_number_of_packets,
params.c_s00_axis_tdata_width))
return Cosimulation("vvp -m ../iverilog/myhdl.vpi RANCNetwork.o",
**input_ports._asdict(), **output_ports._asdict())
def v_rf(readA, readB, write, rAddrA, rAddrB, wAddr, writeSignal, clock, reset,
registers):
cmd = 'iverilog -o %s %s %s' % (RF_cosim_o, RF_cosim_v, RF_v)
os.system(cmd)
return Cosimulation('vvp -m %s %s' % (myhdl_vpi, RF_cosim_o),
readA=readA,
readB=readB,
write=write,
rAddrA=rAddrA,
rAddrB=rAddrB,
wAddr=wAddr,
writeSignal=writeSignal,
clock=clock,
reset=reset,
regOut0=registers[0],
regOut1=registers[1],
regOut2=registers[2],
regOut3=registers[3],
regOut4=registers[4],
regOut5=registers[5],
regOut6=registers[6],
regOut7=registers[7],
regOut8=registers[8],
regOut9=registers[9],
regOut10=registers[10],
regOut11=registers[11],
regOut12=registers[12],
regOut13=registers[13],
regOut14=registers[14],
regOut15=registers[15],
regOut16=registers[16],
regOut17=registers[17],
regOut18=registers[18],
regOut19=registers[19],
regOut20=registers[20],
regOut21=registers[21],
regOut22=registers[22],
regOut23=registers[23],
regOut24=registers[24],
regOut25=registers[25],
regOut26=registers[26],
regOut27=registers[27],
regOut28=registers[28],
regOut29=registers[29],
regOut30=registers[30],
regOut31=registers[31])
def simulate(self, clks=None):
"""
Run a test bench simulation.
"""
if clks is None:
clks = 200
self.dut = Cosimulation(
"vvp -m ./myhdl.vpi fftexec",
clk=self.clk,
rst_n=self.rst_n,
din=self.in_data,
din_nd=self.in_nd,
dout=self.out_data,
dout_nd=self.out_nd,
overflow=self.overflow,
)
sim = Simulation(self.dut, self.clk_driver(), self.control())
sim.run(self.half_period * 2 * clks)
def deflate(i_mode, o_done, i_data, o_iprogress, o_oprogress, o_byte,
i_waddr, i_raddr, clk, reset):
print("Cosimulation")
cmd = "iverilog -o deflate " + \
"deflate.v " + \
"tb_deflate.v " # "dump.v "
os.system(cmd)
return Cosimulation("vvp -m ./myhdl deflate",
i_mode=i_mode,
o_done=o_done,
i_data=i_data,
o_iprogress=o_iprogress,
o_oprogress=o_oprogress,
o_byte=o_byte,
i_waddr=i_waddr,
i_raddr=i_raddr,
clk=clk,
reset=reset)
def bin2gray(B, G, width):
return Cosimulation(cmd % width, B=B, G=G)
def inc(count, enable, clock, reset, n):
os.system('vlog -quiet +define+n=%s ../../test/verilog/inc.v' % (n))
os.system('vlog -quiet +define+n=%s ../../test/verilog/dut_inc.v' % (n))
return Cosimulation(cmd, **locals())
def dff_clkout(clkout, q, d, clk, reset):
os.system(cmd % vhdl_srcroute)
return Cosimulation("%s/dut_dff_clkout" % vhdl_srcroute, **locals())
def setupCosimulationCver(**kwargs):
name = kwargs['name']
cmd = "cver -q +loadvpi=../../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap " + \
"%s.v tb_%s.v " % (name, name)
return Cosimulation(cmd, **kwargs)
def dff(q, d, clk, reset):
os.system(cmd)
return Cosimulation("vvp -m ../myhdl.vpi dff.o", **locals())
def dff(q, d, clk, reset):
return Cosimulation(cmd, **locals())
from __future__ import generators
from __future__ import print_function
from myhdl import Signal, Simulation, Cosimulation
from myhdl import delay, intbv, now
import os
cmd = "iverilog -o tb_test.o ./tb_test.v "
os.system(cmd)
a = Signal(intbv(1))
b = Signal(intbv(2))
c = Signal(intbv(3))
cosim = Cosimulation("vvp -v -m ../myhdl.vpi tb_test.o", a=a, b=b, c=c)
def stimulus(a, b):
for i in range(10):
yield delay(10)
# print "Python a=%s b=%s" % (a, b)
a.next = a + 1
b.next = b + 2
def response(c):
while 1:
yield c
print("Python: %s %s %s %s" % (now(), c, a, b))
def bin2gray(B, G, width):
os.system(cmd % width)
return Cosimulation("vvp -m ../myhdl.vpi bin2gray.o", B=B, G=G)
def speechfifo(i_clk, o_uart_tx):
''' A Cosimulation object, used to simulate Verilog modules '''
os.system('iverilog -o speechfifo.vvp speechfifo.v speechfifo_tb.v')
return Cosimulation('vvp -m ./myhdl.vpi speechfifo.vvp', i_clk=i_clk, o_uart_tx=o_uart_tx)
def dff_clkout(clkout, q, d, clk, reset):
os.system('vlog -quiet ../../test/verilog/dff_clkout.v')
os.system('vlog -quiet ../../test/verilog/dut_dff_clkout.v')
return Cosimulation(cmd, **locals())
def cosim_dut(self, cosim_name, fifo_args, whitebox_args):
"""Get the ``Cosimulation`` object.
:param cosim_name: The name of the cosimulation.
:param fifo_args: A dictionary of args to pass to the FIFOs.
:param whitebox_args: A dictionary of args to pass to the Whitebox Peripheral.
:returns: A `myhdl.Cosimulation` object.
"""
bus_pclk = self.bus.pclk
bus_paddr = self.bus.paddr
bus_psel = self.bus.psel
bus_penable = self.bus.penable
bus_pwrite = self.bus.pwrite
bus_pwdata = self.bus.pwdata
bus_pslverr = self.bus.pslverr
bus_pready = self.bus.pready
bus_prdata = self.bus.prdata
clearn = ResetSignal(0, 0, async=True)
fifo_depth = fifo_args['depth']
tx_fifo_re = Signal(bool(False))
tx_fifo_rclk = self.dac_clock
tx_fifo_rdata = Signal(intbv(0)[32:])
tx_fifo_we = Signal(bool(False))
tx_fifo_wclk = self.bus.pclk
tx_fifo_wdata = Signal(intbv(0)[32:])
tx_fifo_full = Signal(bool(False))
tx_fifo_afull = Signal(bool(False))
tx_fifo_empty = Signal(bool(True))
tx_fifo_aempty = Signal(bool(True))
tx_fifo_afval = Signal(intbv(fifo_depth - 1)[10:])
tx_fifo_aeval = Signal(intbv(0)[10:])
tx_fifo_wack = Signal(bool(False))
tx_fifo_dvld = Signal(bool(False))
tx_fifo_overflow = Signal(bool(False))
tx_fifo_underflow = Signal(bool(False))
tx_fifo_rdcnt = Signal(intbv(0, min=0, max=fifo_depth + 1))
tx_fifo_wrcnt = Signal(intbv(fifo_depth, min=0, max=fifo_depth + 1))
tx_fifo_signals = (clearn, tx_fifo_re, tx_fifo_rclk, tx_fifo_rdata,
tx_fifo_we, tx_fifo_wclk, tx_fifo_wdata,
tx_fifo_full, tx_fifo_afull, tx_fifo_empty,
tx_fifo_aempty, tx_fifo_afval, tx_fifo_aeval,
tx_fifo_wack, tx_fifo_dvld, tx_fifo_overflow,
tx_fifo_underflow, tx_fifo_rdcnt, tx_fifo_wrcnt)
tx_fifo = fifo(*tx_fifo_signals, **fifo_args)
rx_fifo_depth = fifo_args['depth']
rx_fifo_re = Signal(bool(False))
rx_fifo_rclk = self.bus.pclk
rx_fifo_rdata = Signal(intbv(0)[32:])
rx_fifo_we = Signal(bool(False))
rx_fifo_wclk = self.dac_clock
rx_fifo_wdata = Signal(intbv(0)[32:])
rx_fifo_full = Signal(bool(False))
rx_fifo_afull = Signal(bool(False))
rx_fifo_empty = Signal(bool(True))
rx_fifo_aempty = Signal(bool(True))
rx_fifo_afval = Signal(intbv(fifo_depth - 1)[10:])
rx_fifo_aeval = Signal(intbv(0)[10:])
rx_fifo_wack = Signal(bool(False))
rx_fifo_dvld = Signal(bool(False))
rx_fifo_overflow = Signal(bool(False))
rx_fifo_underflow = Signal(bool(False))
rx_fifo_rdcnt = Signal(intbv(0, min=0, max=fifo_depth + 1))
rx_fifo_wrcnt = Signal(intbv(fifo_depth, min=0, max=fifo_depth + 1))
rx_fifo_signals = (clearn, rx_fifo_re, rx_fifo_rclk, rx_fifo_rdata,
rx_fifo_we, rx_fifo_wclk, rx_fifo_wdata,
rx_fifo_full, rx_fifo_afull, rx_fifo_empty,
rx_fifo_aempty, rx_fifo_afval, rx_fifo_aeval,
rx_fifo_wack, rx_fifo_dvld, rx_fifo_overflow,
rx_fifo_underflow, rx_fifo_rdcnt, rx_fifo_wrcnt)
rx_fifo = fifo(*rx_fifo_signals, **fifo_args)
config_file = tempfile.NamedTemporaryFile(delete=False)
config_file.write('+define+COSIM_NAME="%s"' % (cosim_name, ))
config_file.close()
cmd = 'iverilog -o %s.v -c %s whitebox.v whitebox_reset.v /home/testa/whitebox/hdl/cosim_whitebox.v' % (
cosim_name, config_file.name)
os.system(cmd)
fir_coeff_ram_addr = self.fir_coeff_ram.port['a'].addr
fir_coeff_ram_din0 = self.fir_coeff_ram.port['a'].din[0]
fir_coeff_ram_din1 = self.fir_coeff_ram.port['a'].din[1]
fir_coeff_ram_width0 = self.fir_coeff_ram.port['a'].width0
fir_coeff_ram_width1 = self.fir_coeff_ram.port['a'].width1
fir_coeff_ram_pipe = self.fir_coeff_ram.port['a'].pipe
fir_coeff_ram_wmode = self.fir_coeff_ram.port['a'].wmode
fir_coeff_ram_blk = self.fir_coeff_ram.port['a'].blk
fir_coeff_ram_wen = self.fir_coeff_ram.port['a'].wen
fir_coeff_ram_clk = self.fir_coeff_ram.port['a'].clk
fir_coeff_ram_dout0 = self.fir_coeff_ram.port['a'].dout[0]
fir_coeff_ram_dout1 = self.fir_coeff_ram.port['a'].dout[1]
fir_load_coeff_ram_addr = self.fir_coeff_ram.port['b'].addr
fir_load_coeff_ram_din0 = self.fir_coeff_ram.port['b'].din[0]
fir_load_coeff_ram_din1 = self.fir_coeff_ram.port['b'].din[1]
fir_load_coeff_ram_width0 = self.fir_coeff_ram.port['b'].width0
fir_load_coeff_ram_width1 = self.fir_coeff_ram.port['b'].width1
fir_load_coeff_ram_pipe = self.fir_coeff_ram.port['b'].pipe
fir_load_coeff_ram_wmode = self.fir_coeff_ram.port['b'].wmode
fir_load_coeff_ram_blk = self.fir_coeff_ram.port['b'].blk
fir_load_coeff_ram_wen = self.fir_coeff_ram.port['b'].wen
fir_load_coeff_ram_clk = self.fir_coeff_ram.port['b'].clk
fir_load_coeff_ram_dout0 = self.fir_coeff_ram.port['b'].dout[0]
fir_load_coeff_ram_dout1 = self.fir_coeff_ram.port['b'].dout[1]
fir_delay_line_i_ram_addr = self.fir_delay_line_i_ram.port['a'].addr
fir_delay_line_i_ram_din = self.fir_delay_line_i_ram.port['a'].din
fir_delay_line_i_ram_width0 = self.fir_delay_line_i_ram.port[
'a'].width0
fir_delay_line_i_ram_width1 = self.fir_delay_line_i_ram.port[
'a'].width1
fir_delay_line_i_ram_pipe = self.fir_delay_line_i_ram.port['a'].pipe
fir_delay_line_i_ram_wmode = self.fir_delay_line_i_ram.port['a'].wmode
fir_delay_line_i_ram_blk = self.fir_delay_line_i_ram.port['a'].blk
fir_delay_line_i_ram_wen = self.fir_delay_line_i_ram.port['a'].wen
fir_delay_line_i_ram_clk = self.fir_delay_line_i_ram.port['a'].clk
fir_delay_line_i_ram_dout = self.fir_delay_line_i_ram.port['a'].dout
fir_delay_line_q_ram_addr = self.fir_delay_line_q_ram.port['a'].addr
fir_delay_line_q_ram_din = self.fir_delay_line_q_ram.port['a'].din
fir_delay_line_q_ram_width0 = self.fir_delay_line_q_ram.port[
'a'].width0
fir_delay_line_q_ram_width1 = self.fir_delay_line_q_ram.port[
'a'].width1
fir_delay_line_q_ram_pipe = self.fir_delay_line_q_ram.port['a'].pipe
fir_delay_line_q_ram_wmode = self.fir_delay_line_q_ram.port['a'].wmode
fir_delay_line_q_ram_blk = self.fir_delay_line_q_ram.port['a'].blk
fir_delay_line_q_ram_wen = self.fir_delay_line_q_ram.port['a'].wen
fir_delay_line_q_ram_clk = self.fir_delay_line_q_ram.port['a'].clk
fir_delay_line_q_ram_dout = self.fir_delay_line_q_ram.port['a'].dout
whitebox_test = Cosimulation(
'vvp -m ./myhdl.vpi %s.v' % (cosim_name, ),
resetn=self.bus.presetn,
pclk=self.bus.pclk,
paddr=self.bus.paddr,
psel=self.bus.psel,
penable=self.bus.penable,
pwrite=self.bus.pwrite,
pwdata=self.bus.pwdata,
pready=self.bus.pready,
prdata=self.bus.prdata,
#pslverr=self.bus.pslverr,
clearn=clearn,
clear_enable=self.clear_enable,
dac_clock=self.dac_clock,
dac2x_clock=self.dac2x_clock,
dac_en=self.dac_en,
dac_data=self.dac_data,
adc_idata=self.adc_idata,
adc_qdata=self.adc_qdata,
tx_status_led=self.tx_status_led,
tx_dmaready=self.tx_dmaready,
rx_status_led=self.rx_status_led,
rx_dmaready=self.rx_dmaready,
tx_fifo_re=tx_fifo_re,
tx_fifo_rclk=tx_fifo_rclk,
tx_fifo_rdata=tx_fifo_rdata,
tx_fifo_we=tx_fifo_we,
tx_fifo_wclk=tx_fifo_wclk,
tx_fifo_wdata=tx_fifo_wdata,
tx_fifo_full=tx_fifo_full,
tx_fifo_afull=tx_fifo_afull,
tx_fifo_empty=tx_fifo_empty,
tx_fifo_aempty=tx_fifo_aempty,
tx_fifo_afval=tx_fifo_afval,
tx_fifo_aeval=tx_fifo_aeval,
tx_fifo_wack=tx_fifo_wack,
tx_fifo_dvld=tx_fifo_dvld,
tx_fifo_overflow=tx_fifo_overflow,
tx_fifo_underflow=tx_fifo_underflow,
tx_fifo_rdcnt=tx_fifo_rdcnt,
tx_fifo_wrcnt=tx_fifo_wrcnt,
rx_fifo_re=rx_fifo_re,
rx_fifo_rclk=rx_fifo_rclk,
rx_fifo_rdata=rx_fifo_rdata,
rx_fifo_we=rx_fifo_we,
rx_fifo_wclk=rx_fifo_wclk,
rx_fifo_wdata=rx_fifo_wdata,
rx_fifo_full=rx_fifo_full,
rx_fifo_afull=rx_fifo_afull,
rx_fifo_empty=rx_fifo_empty,
rx_fifo_aempty=rx_fifo_aempty,
rx_fifo_afval=rx_fifo_afval,
rx_fifo_aeval=rx_fifo_aeval,
rx_fifo_wack=rx_fifo_wack,
rx_fifo_dvld=rx_fifo_dvld,
rx_fifo_overflow=rx_fifo_overflow,
rx_fifo_underflow=rx_fifo_underflow,
rx_fifo_rdcnt=rx_fifo_rdcnt,
rx_fifo_wrcnt=rx_fifo_wrcnt,
fir_coeff_ram_addr=fir_coeff_ram_addr,
fir_coeff_ram_din0=fir_coeff_ram_din0,
fir_coeff_ram_din1=fir_coeff_ram_din1,
fir_coeff_ram_width0=fir_coeff_ram_width0,
fir_coeff_ram_width1=fir_coeff_ram_width1,
fir_coeff_ram_pipe=fir_coeff_ram_pipe,
fir_coeff_ram_wmode=fir_coeff_ram_wmode,
fir_coeff_ram_blk=fir_coeff_ram_blk,
fir_coeff_ram_wen=fir_coeff_ram_wen,
fir_coeff_ram_clk=fir_coeff_ram_clk,
fir_coeff_ram_dout0=fir_coeff_ram_dout0,
fir_coeff_ram_dout1=fir_coeff_ram_dout1,
fir_load_coeff_ram_addr=fir_load_coeff_ram_addr,
fir_load_coeff_ram_din0=fir_load_coeff_ram_din0,
fir_load_coeff_ram_din1=fir_load_coeff_ram_din1,
fir_load_coeff_ram_width0=fir_load_coeff_ram_width0,
fir_load_coeff_ram_width1=fir_load_coeff_ram_width1,
fir_load_coeff_ram_pipe=fir_load_coeff_ram_pipe,
fir_load_coeff_ram_wmode=fir_load_coeff_ram_wmode,
fir_load_coeff_ram_blk=fir_load_coeff_ram_blk,
fir_load_coeff_ram_wen=fir_load_coeff_ram_wen,
fir_load_coeff_ram_clk=fir_load_coeff_ram_clk,
fir_load_coeff_ram_dout0=fir_load_coeff_ram_dout0,
fir_load_coeff_ram_dout1=fir_load_coeff_ram_dout1,
fir_delay_line_i_ram_addr=fir_delay_line_i_ram_addr,
fir_delay_line_i_ram_din=fir_delay_line_i_ram_din,
fir_delay_line_i_ram_width0=fir_delay_line_i_ram_width0,
fir_delay_line_i_ram_width1=fir_delay_line_i_ram_width1,
fir_delay_line_i_ram_pipe=fir_delay_line_i_ram_pipe,
fir_delay_line_i_ram_wmode=fir_delay_line_i_ram_wmode,
fir_delay_line_i_ram_blk=fir_delay_line_i_ram_blk,
fir_delay_line_i_ram_wen=fir_delay_line_i_ram_wen,
fir_delay_line_i_ram_clk=fir_delay_line_i_ram_clk,
fir_delay_line_i_ram_dout=fir_delay_line_i_ram_dout,
fir_delay_line_q_ram_addr=fir_delay_line_q_ram_addr,
fir_delay_line_q_ram_din=fir_delay_line_q_ram_din,
fir_delay_line_q_ram_width0=fir_delay_line_q_ram_width0,
fir_delay_line_q_ram_width1=fir_delay_line_q_ram_width1,
fir_delay_line_q_ram_pipe=fir_delay_line_q_ram_pipe,
fir_delay_line_q_ram_wmode=fir_delay_line_q_ram_wmode,
fir_delay_line_q_ram_blk=fir_delay_line_q_ram_blk,
fir_delay_line_q_ram_wen=fir_delay_line_q_ram_wen,
fir_delay_line_q_ram_clk=fir_delay_line_q_ram_clk,
fir_delay_line_q_ram_dout=fir_delay_line_q_ram_dout,
)
return tx_fifo, rx_fifo, self.fir_coeff_ram.rama, self.fir_coeff_ram.ramb, self.fir_delay_line_i_ram.ram, self.fir_delay_line_q_ram.ram, whitebox_test