def parse_p2g(lines):
"""Parse p2g format graph from string or iterable. Returns an XDiGraph."""
if is_string_like(lines): lines = iter(lines.split('\n'))
lines = iter([line.rstrip('\n') for line in lines])
description = lines.next()
# are multiedges (parallel edges) allowed?
G = networkx.XDiGraph(name=description, selfloops=True)
nnodes, nedges = map(int, lines.next().split())
nodelabel = {}
nbrs = {}
# loop over the nodes keeping track of node labels and out neighbors
# defer adding edges until all node labels are known
for i in range(nnodes):
n = lines.next()
nodelabel[i] = n
G.add_node(n)
nbrs[n] = map(int, lines.next().split())
# now we know all of the node labels so we can add the edges
# with the correct labels
for n in G:
for nbr in nbrs[n]:
G.add_edge(n, nodelabel[nbr])
return G
def compute(self, dataset_pool):
edges = dataset_pool.get_dataset('edge')
edges.get_graph(create_using=networkx.XDiGraph(), edgetype=int)
household_x_parcels = self.get_dataset()
home_parcel = household_x_parcels.get_2d_dataset_attribute(
"parcel_id").astype(int32)
n, m = home_parcel.shape
n_index = household_x_parcels.get_index(1)
if n_index is None:
n_index = arange(n)
work_parcel = household_x_parcels.get_dataset(
1).get_attribute_by_index(self.work_parcel_id,
n_index).astype(int32)
pairs = map(lambda x, y: (x, y.tolist()), work_parcel, home_parcel)
results = array(
edges.compute_dijkstra_path_length(
pairs,
default_value=self.default_value,
# show_progress=True
))
return array(results)
def stochastic(G, inplace=False):
"""Return a version of the weighted graph G converted to a (right)
stochastic representation. That is, make all of the weights for the
neighbors of a given node sum to 1.
If inplace=True the conversion is done in place - no copy of the graph is
made. This will destroy the original graph G.
"""
# this is a hack, better handling to come in networkx-0.36
if inplace:
W = G # copy, better be an XGraph
else:
if G.is_directed():
W = NX.XDiGraph(G) # make a new XDiGraph
else:
W = NX.XGraph(G) # make a new XGraph
for (u, v, d) in W.edges():
if d is None:
W.add_edge(u, v, 1.0)
# exposing graph/digraph internals here
for n in W:
print "W.adj[n].values():", W.adj[n].values()
deg = float(sum(W.adj[n].values()))
for p in W.adj[n]:
W.adj[n][p] /= deg
return W
def collectDependencies(cls,sentence):
tmp = sentence.find('sentenceanalyses')
# collect dep.edges
tmp2 = [x for x in tmp.getiterator('parse')
if x.attrib['tokenizer']=='Charniak-Lease'][0]
G = NX.XDiGraph()
for x in tmp2.findall('dependency'):
G.add_edge(x.attrib['t1'],x.attrib['t2'],x.attrib['type'])
return(G)
def compute(self, dataset_pool):
edges = dataset_pool.get_dataset('edge')
edges.get_graph(create_using=networkx.XDiGraph(), edgetype=int)
persons = self.get_dataset()
homes = persons.get_attribute("home_parcel_id").astype(int32)
workplaces = persons.get_attribute("work_place_parcel_id").astype(
int32)
pairs = map(lambda x, y: (x, y), workplaces, homes)
results = edges.compute_dijkstra_path_length(
pairs, default_value=self.default_value)
return results
def __init__(self, instructions, subInstructions, memPenaltyFactor=2):
"""memPenaltyFactor represent how much the heuristic has to take
into account memory consumption: the lower the more memory is
consumed by the created decoder."""
self.memPenaltyFactor = memPenaltyFactor
self.instrId = {}
self.instrName = {}
self.instrSub = {}
self.instrPattern = []
self.invalid_instr = None
# Now, given the frequencies, I compute the probabilities
# for each instruction
self.minFreq = 0
self.totalCount = 1
if instructions:
self.minFreq = instructions.values()[0].frequency
self.totalCount = 0
for instr in instructions.values():
self.totalCount += instr.frequency
if instr.frequency < self.minFreq:
self.minFreq = instr.frequency
# for each instruction I get the ID and the machine
# code
self.instrNum = len(instructions)
# Note how the most significant bit of the bitstring is
# the first one of instr.bitstring. So, in order to correctly
# perform the computation I reverse the bistring and perform
# the calculation. At the end, when it is time to print the
# the decoder into C++ code, I reverse again the patterns so
# that the decoder is correctly printed
for name, instr in instructions.items():
if not name in subInstructions.keys():
revBitstring = list(instr.bitstring)
revBitstring.reverse()
self.instrName[instr.id] = name
self.instrSub[instr.id] = instr.subInstructions
self.instrId[instr.id] = (revBitstring,
float(instr.frequency) /
float(self.totalCount))
self.instrPattern.append(
(revBitstring,
float(instr.frequency) / float(self.totalCount)))
if nxVersion < 0.99:
self.decodingTree = NX.XDiGraph()
else:
self.decodingTree = NX.DiGraph()
self.computeIllegalBistreams()
self.computeDecoder()
def nx_graph(self):
"""Convert the data in a ``nodelist`` into a networkx labeled directed graph."""
import networkx as NX
nx_nodelist = list(range(1, len(self.nodes)))
nx_edgelist = [(n, self._hd(n), self._rel(n)) for n in nx_nodelist
if self._hd(n)]
self.nx_labels = {}
for n in nx_nodelist:
self.nx_labels[n] = self.nodes[n]['word']
g = NX.XDiGraph()
g.add_nodes_from(nx_nodelist)
g.add_edges_from(nx_edgelist)
return g
def build_adv_flow_graph(G, seeds):
"""Build a flow graph from a graph, as described in the Advogato
trust metric paper:
* add supersink
* for every node: add N_node and P_node
* set initial flow to 0
"""
# This also ensures that there are no nodes named "source" or "supersink"
neg, pos = lambda n: "N" + str(n), lambda n: "P" + str(n)
G_flow = networkx.XDiGraph()
G_flow.add_node("source")
G_flow.add_node("supersink")
for src in seeds:
if not src in G:
seeds.remove(src)
distance_map = {}
for src in seeds:
# build the distance map, we don't want to add a new source node to G,
# so we have to get a temp_dist_map for every seed node
temp_dist_map = path.single_source_shortest_path_length(G, src)
for n, d in temp_dist_map.items():
if distance_map.has_key(n):
distance_map[n] = min(distance_map[n], d)
else:
distance_map[n] = d
for n in G.nodes_iter():
cap_value = 1
if distance_map.has_key(n):
dist = distance_map[n]
if dist <= 5:
cap_value = cap_dict[dist]
if n in seeds:
# it's not clear yet if this is actually what is happening
# in tmetric.c
G_flow.add_edge("source", neg(n), {'flow': 0})
assert cap_value == 800
G_flow.add_edge(neg(n), pos(n), {'cap': cap_value - 1, 'flow': 0})
G_flow.add_edge(neg(n), "supersink", {'cap': 1, 'flow': 0})
for e in G.edges_iter():
G_flow.add_edge(pos(e[0]), neg(e[1]), {'flow': 0})
return G_flow
def parse_pajek(lines):
"""Parse pajek format graph from string or iterable.."""
import shlex
if is_string_like(lines): lines = iter(lines.split('\n'))
lines = iter([line.rstrip('\n') for line in lines])
G = networkx.XDiGraph(selfloops=True) # are multiedges allowed in Pajek?
G.node_attr = {} # dictionary to hold node attributes
directed = True # assume this is a directed network for now
while lines:
try:
l = lines.next()
except: #EOF
break
if l.startswith("*network"):
label, name = l.split()
G.name = name
if l.startswith("*vertices"):
nodelabels = {}
l, nnodes = l.split()
for i in range(int(nnodes)):
splitline = shlex.split(lines.next())
id, label, x, y, shape = splitline[0:5]
G.add_node(label)
nodelabels[id] = label
G.node_attr[label] = {'id': id, 'x': x, 'y': y, 'shape': shape}
extra_attr = zip(splitline[5::2], splitline[6::2])
G.node_attr[label].update(extra_attr)
if l.startswith("*edges") or l.startswith("*arcs"):
if l.startswith("*edge"):
G = networkx.XGraph(G) # switch from digraph to graph
for l in lines:
splitline = shlex.split(l)
ui, vi, w = splitline[0:3]
u = nodelabels.get(ui, ui)
v = nodelabels.get(vi, vi)
edge_data = {'value': float(w)}
extra_attr = zip(splitline[3::2], splitline[4::2])
edge_data.update(extra_attr)
G.add_edge(u, v, edge_data)
return G
def graphFromList(self):
""" This function constructs a weighted directed graph from the
list that depicts the map using the following scheme:
Left A, Right B -> add (A, B, 1)
Left B, Right A -> add (B, A, 1)
Up A, Down B -> add (A, B,-1)
Up B, Down A -> add (B, A,-1)
We then add all similar edges together, so for instance
(A, B, 1) and (A, B, 1) -> (A, B, 2)
but *NOT*
(A, B, 1) and (A, B, -1) -> (A, B, 0)
"""
self.G = networkx.XDiGraph(selfloops=False, multiedges=True)
L = self.MapList
progress = -1
print "Generating the graph: "
# Now add for every Cartesian crossing an edge (or a value) in G
for i in range(len(L) - 1):
for j in range(len(L[0]) - 1):
self.addEdge(L[i][j], L[i][j + 1], 1) # L-R, +1
self.addEdge(L[i][j], L[i + 1][j], -1) # U-D, -1
# Calculate the progress, and print it to the screen.
p = ((j + i * len(L)) * 100) / (len(L) * len(L[0]))
if progress != p:
progress = p
self.printProgress(progress)
# What remains is the bottom and right line of edges:
for j in range(len(L[0]) - 1):
self.addEdge(L[len(L) - 1][j], L[len(L) - 1][j + 1], 1)
for i in range(len(L) - 1):
self.addEdge(L[i][len(L[0]) - 1], L[i + 1][len(L[0]) - 1], -1)
# Now show 100% progress and say we're done.
self.printProgress(100)
print "Done!"
def getCPPRegisters(self, trace, combinedTrace, model, namespace):
"""Creates a container register bank for all registers, register banks,
aliases and alias register banks of a processor. This encapsulates the
register instantiation details (defining fields, etc) away from the
processor. It also eases passes the registers to instructions, since only
the container class needs to be passed.
@see trap/runtime/modules/register/register_bank.hpp for a discussion."""
#---------------------------------------------------------------------------
## @name Preprocessing
# @{
# Abstraction Level
abstractionType = cxx_writer.Type(
'trap::amba_layer_ids',
'register_abstraction.hpp') #'amba_parameters.h')
abstraction = ''
if model.startswith('acc'):
abstraction = 'trap::amba_CT'
elif model.startswith('func'):
if model.endswith('AT'):
abstraction = 'trap::amba_AT'
else:
abstraction = 'trap::amba_LT'
# Register Types
regLen = 0
# Determine the register with the largest bitwidth.
for reg in self.regs + self.regBanks:
if reg.bitWidth > regLen:
regLen = reg.bitWidth
from isa import resolveBitType
global registerInterfaceType, registerType, aliasType
registerMaxBitwidth = resolveBitType('BIT<' + str(regLen) + '>')
registerFieldType = cxx_writer.TemplateType('trap::RegisterField',
[registerMaxBitwidth],
'modules/register.hpp')
registerInterfaceType = cxx_writer.TemplateType(
'trap::RegisterInterface', [registerMaxBitwidth, registerFieldType],
'modules/register.hpp')
registerType = cxx_writer.TemplateType('trap::Register',
[registerMaxBitwidth],
'modules/register.hpp')
aliasType = cxx_writer.TemplateType('trap::RegisterAlias',
[registerMaxBitwidth],
'modules/register.hpp')
# Alias Register and Alias Register Bank Initialization Order
# Aliases that depend on each other need to be initialized in order. We
# therefore create a dependency graph for both alias registers and alias
# register banks.
if nxVersion < 0.99:
aliasUnsortedGraph = NX.XDiGraph()
else:
aliasUnsortedGraph = NX.DiGraph()
for alias in self.aliasRegs + self.aliasRegBanks:
aliasUnsortedGraph.add_node(alias)
for alias in self.aliasRegs + self.aliasRegBanks:
aliasPredecessors = []
if isinstance(alias.initAlias, str):
bracketIdx = alias.initAlias.find('[')
if bracketIdx > 0:
aliasPredecessors.append(alias.initAlias[:bracketIdx])
else:
aliasPredecessors.append(alias.initAlias)
else:
for aliasPredecessor in alias.initAlias:
bracketIdx = aliasPredecessor.find('[')
if bracketIdx > 0:
aliasPredecessors.append(aliasPredecessor[:bracketIdx])
else:
aliasPredecessors.append(aliasPredecessor)
for aliasPredecessor in aliasPredecessors:
for aliasTarget in self.aliasRegs + self.aliasRegBanks:
if aliasPredecessor == aliasTarget.name:
aliasUnsortedGraph.add_edge(aliasTarget, alias)
# Check for circular dependencies.
# NOTE: We might have some false positives here. We discarded indices for
# banks, so a perfectly valid REGS1[x1]->REGS2[y1]; REGS2[y2]->REGS1[x2]
# with ((x1 != x2) || (y1 != y2)) will be stored as REG1->REGS2;
# REGS2->REGS1 and raise an error.
# In reality, this will probably never happen anyway, since the visibility
# of banks as a whole tends to be hierarchical.
if not NX.is_directed_acyclic_graph(aliasUnsortedGraph):
raise Exception(
'Detected circular dependence in alias initializations.')
# Sort dependency graph.
global aliasGraph
aliasGraph = NX.topological_sort(aliasUnsortedGraph)
registerElements = []
# reg_clock_cycle()
# @see getPipeClockCycleFunction.
pipeClockCycleFunction = getPipeClockCycleFunction(self,
registerMaxBitwidth)
if model.startswith('acc'):
registerElements.append(pipeClockCycleFunction)
## @} Preprocessing
#---------------------------------------------------------------------------
## @name Attributes and Initialization
# @{
from processor import extractRegInterval
registerMembers = []
registerCtorParams = []
registerCtorInit = []
registerCtorCode = ''
# Registers
registerCtorCode += '// Initialize registers.\n'
for reg in self.regs:
# Attribute Declaration
registerMembers.append(
cxx_writer.Attribute(reg.name.lower(), registerType, 'public'))
# Constructor Parameters
if isinstance(reg.constValue, str):
if reg.constValue not in [
param.name for param in registerCtorParams
]:
registerCtorParams.append(
cxx_writer.Parameter(reg.constValue, registerMaxBitwidth))
# Iterable element, i.e. initialization with a constant and an offset.
# TODO: Some of the default values are processor variables such as
# ENTRY_POINT and MPROC_ID. These are sadly globals and set by the
# loader at some point. The current solution passes uninitialized
# values. There are several options:
# 1. Force program loading before processor construction. Easy but
# limits the user.
# 2. Keep the current proc if, but pass a reference instead of a value.
# Create a stub bool = 0 for all other registers. Minimal impact but
# ugly.
# 3. Create processor.load(), which sets both the processor vars and
# resets the registers. Works for the PC, but not for others. Also
# still ugly, as the register should do its own resetting.
# 4. Create a processor.load(), which calls a register.
# set_reset_value(). 1) Clean processor if, 2) keeps the reset value
# in the register and 3) works for both const and non-const reset
# values.
if isinstance(reg.defValue, tuple):
if reg.defValue[0] not in [
param.name for param in registerCtorParams
]:
registerCtorParams.append(
cxx_writer.Parameter(str(reg.defValue[0]),
registerMaxBitwidth))
elif isinstance(reg.defValue, str):
if reg.defValue not in [
param.name for param in registerCtorParams
]:
registerCtorParams.append(
cxx_writer.Parameter(str(reg.defValue),
registerMaxBitwidth))
# Constructor Initialization List
# name, abstraction
Code = '("' + reg.name.lower() + '", ' + abstraction + ', '
# is_const
if reg.constValue: Code += 'true, '
else: Code += 'false, '
# offset
if reg.offset: Code += str(reg.offset) + ', '
else: Code += '0, '
# delay
if reg.delay: Code += str(reg.delay) + ', '
else: Code += '0, '
# reset_val
if reg.constValue != None:
try:
Code += hex(reg.constValue)
except TypeError:
Code += str(reg.constValue)
elif reg.defValue != None:
# Iterable element, i.e. initialization with a constant and an
# offset.
if isinstance(reg.defValue, tuple):
Code += str(reg.defValue[0]) + ' + '
try:
Code += hex(reg.defValue[1])
except TypeError:
Code += str(reg.defValue[1])
else:
try:
Code += hex(reg.defValue)
except TypeError:
Code += str(reg.defValue)
else:
Code += '0'
Code += ', '
# num_pipe_stages
if self.pipes: Code += str(len(self.pipes))
else: Code += '1'
if model.startswith('acc'):
if reg.isGlobal:
Code += ', NULL, true'
elif reg.wbStageOrder:
registerClockCycleFunction = getRegisterClockCycleFunction(
self, reg.name, reg.wbStageOrder, registerMaxBitwidth)
registerElements.append(registerClockCycleFunction)
Code += ', ' + registerClockCycleFunction.name
elif pipeClockCycleFunction:
Code += ', ' + pipeClockCycleFunction.name
Code += ')'
registerCtorInit.append(reg.name.lower() + Code)
# Constructor Body: Add fields
if reg.bitMask:
for registerFieldMaskName, registerFieldMaskPos in reg.bitMask.items(
):
registerCtorCode += reg.name.lower(
) + '.add_field("' + registerFieldMaskName + '", ' + str(
registerFieldMaskPos[1]) + ', ' + str(
registerFieldMaskPos[0]) + ');\n'
registerCtorCode += '\n'
# Register Banks
registerCtorCode += '// Initialize register banks.\n'
for regBank in self.regBanks:
# Attribute Declaration
registerMembers.append(
cxx_writer.Attribute(
regBank.name.lower() + '[' + str(regBank.numRegs) + ']',
registerType, 'public'))
# Constructor Parameters
for regConstValue in regBank.constValue.values():
if isinstance(regConstValue, str):
if regConstValue not in [
param.name for param in registerCtorParams
]:
registerCtorParams.append(
cxx_writer.Parameter(regConstValue,
registerMaxBitwidth))
for regDefaultValue in regBank.defValues:
# Iterable element, i.e. initialization with a constant and an
# offset.
if isinstance(regDefaultValue, tuple):
if regDefaultValue[0] not in [
param.name for param in registerCtorParams
]:
registerCtorParams.append(
cxx_writer.Parameter(str(regDefaultValue[0]),
registerMaxBitwidth))
elif isinstance(regDefaultValue, str):
if regDefaultValue not in [
param.name for param in registerCtorParams
]:
registerCtorParams.append(
cxx_writer.Parameter(str(regDefaultValue),
registerMaxBitwidth))
# Constructor Initialization List
Code = ''
for reg in range(0, regBank.numRegs):
# name, abstraction
Code += '{"' + regBank.name.lower() + '[' + str(
reg) + ']", ' + abstraction + ', '
# is_const
if regBank.constValue.has_key(reg): Code += 'true, '
else: Code += 'false, '
# offset
if regBank.offset: Code += str(regBank.offset) + ', '
else: Code += '0, '
# delay
if regBank.delay.has_key(reg):
Code += str(regBank.delay[reg]) + ', '
else:
Code += '0, '
# reset_val
if regBank.constValue.has_key(reg):
try:
Code += hex(regBank.constValue[reg])
except TypeError:
Code += str(regBank.constValue[reg])
elif regBank.defValues[reg] != None:
# Iterable element, i.e. initialization with a constant and an
# offset.
if isinstance(regBank.defValues[reg], tuple):
Code += str(regBank.defValues[reg][0]) + ' + '
try:
Code += hex(regBank.defValues[reg][1])
except TypeError:
Code += str(regBank.defValues[reg][1])
else:
try:
Code += hex(regBank.defValues[reg])
except TypeError:
Code += str(regBank.defValues[reg])
else:
Code += '0'
Code += ', '
# num_pipe_stages
if self.pipes: Code += str(len(self.pipes))
else: Code += '1'
if model.startswith('acc'):
if regBank.isGlobal:
Code += ', NULL, true'
elif regBank.wbStageOrder.has_key(reg):
registerClockCycleFunction = getRegisterClockCycleFunction(
self, regBank.name + str(reg),
regBank.wbStageOrder[reg], registerMaxBitwidth)
registerElements.append(registerClockCycleFunction)
Code += ', ' + registerClockCycleFunction.name
elif pipeClockCycleFunction:
Code += ', ' + pipeClockCycleFunction.name
Code += '},\n'
registerCtorInit.append(regBank.name.lower() + ' {' + Code[:-2] + '}')
# Constructor Body: Add fields.
if regBank.bitMask:
registerCtorCode += 'for (unsigned i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
for registerFieldMaskName, registerFieldMaskPos in regBank.bitMask.items(
):
registerCtorCode += regBank.name.lower(
) + '[i].add_field("' + registerFieldMaskName + '", ' + str(
registerFieldMaskPos[1]) + ', ' + str(
registerFieldMaskPos[0]) + ');\n'
registerCtorCode += '}\n\n'
# Alias Registers
for alias in self.aliasRegs:
# Attribute Declaration
#aliasType = cxx_writer.TemplateType('std::reference_wrapper', [registerType], 'functional')
#aliasBankType = cxx_writer.TemplateType('std::vector', [aliasType], 'vector')
registerMembers.append(
cxx_writer.Attribute(alias.name.lower(), aliasType, 'public'))
# Constructor Initialization List
registerCtorInit.append(alias.name.lower() + '("' +
alias.name.lower() + '")')
# Alias Register Banks
for aliasBank in self.aliasRegBanks:
# Attribute Declaration
registerMembers.append(
cxx_writer.Attribute(
aliasBank.name.lower() + '[' + str(aliasBank.numRegs) + ']',
aliasType, 'public'))
# Constructor Initialization List
Code = ''
for aliasIdx in range(0, aliasBank.numRegs):
Code += '{"' + aliasBank.name.lower() + '[' + str(
aliasIdx) + ']"},'
registerCtorInit.append(aliasBank.name.lower() + ' {' + Code[:-1] +
'}')
# Alias Registers and Alias Register Banks
# Constructor Body: Update alias targets.
registerCtorCode += '// Initialize alias registers and alias register banks.\n'
for alias in aliasGraph:
if isinstance(alias.initAlias, str):
regName = alias.initAlias[:alias.initAlias.find('[')]
regRange = extractRegInterval(alias.initAlias)
# REGBANK[n], REGBANK[n:m], REGBANK
if regRange or regName in self.regBanks + self.aliasRegBanks:
aliasIdx = 0
if regRange:
regStart = regRange[0]
regEnd = regRange[1] + 1
else:
regStart = 0
regEnd = reg.numRegs
for regIdx in range(regStart, regEnd):
registerCtorCode += 'this->' + alias.name.lower()
if alias in self.aliasRegBanks:
registerCtorCode += '[' + str(aliasIdx) + ']'
registerCtorCode += '.update_alias(this->' + regName.lower(
) + '[' + str(regIdx) + ']'
if alias in self.aliasRegs:
registerCtorCode += ', ' + str(alias.offset)
elif alias.offsets.has_key(aliasIdx):
registerCtorCode += ', ' + str(alias.offsets[aliasIdx])
else:
registerCtorCode += ', 0'
registerCtorCode += ');\n'
aliasIdx = aliasIdx + 1
# REG
else:
registerCtorCode += 'this->' + alias.name.lower(
) + '.update_alias(this->' + regName.lower()
if alias in self.aliasRegs:
registerCtorCode += ', ' + str(alias.offset)
elif alias.offsets.has_key(aliasIdx):
registerCtorCode += ', ' + str(alias.offsets[aliasIdx])
else:
registerCtorCode += ', 0'
registerCtorCode += ');\n'
else:
aliasIdx = 0
for reg in alias.initAlias:
regName = reg[:reg.find('[')]
regRange = extractRegInterval(reg)
# REGBANK[n], REGBANK[n:m], REGBANK
if regRange or regName in self.regBanks + self.aliasRegBanks:
if regRange:
regStart = regRange[0]
regEnd = regRange[1] + 1
else:
regStart = 0
regEnd = reg.numRegs
for regIdx in range(regStart, regEnd):
registerCtorCode += 'this->' + alias.name.lower(
) + '[' + str(
aliasIdx
) + '].update_alias(this->' + regName.lower(
) + '[' + str(regIdx) + ']'
if alias.offsets.has_key(aliasIdx):
registerCtorCode += ', ' + str(
alias.offsets[aliasIdx])
else:
registerCtorCode += ', 0'
registerCtorCode += ');\n'
aliasIdx = aliasIdx + 1
# REG
else:
registerCtorCode += 'this->' + alias.name.lower(
) + '[' + str(
aliasIdx) + '].update_alias(this->' + regName.lower()
if alias.offsets.has_key(aliasIdx):
registerCtorCode += ', ' + str(alias.offsets[aliasIdx])
else:
registerCtorCode += ', 0'
registerCtorCode += ');\n'
aliasIdx = aliasIdx + 1
# Constructor
registerCtor = cxx_writer.Constructor(cxx_writer.Code(registerCtorCode),
'public',
parameters=registerCtorParams,
initList=registerCtorInit)
## @} Attributes and Initialization
#---------------------------------------------------------------------------
## @name Methods
# Access and Modification: reset(), write(), write_dbg(), write_force()
# Observer: execute_callbacks(), set_stage(), unset_stage(), clock_cycle()
# Information and Helper: operator<<()
# @{
# TODO: Consider a visitor pattern, where the function visiting the
# registers is passed as a parameter.
# Method Bodies: Registers
registerResetCode = '// Reset registers.\n'
registerWriteCode = 'bool ret = true;\n\n// Write registers.\n'
registerWriteDbgCode = 'bool ret = true;\n\n// Write registers.\n'
registerWriteForceCode = 'bool ret = true;\n\n// Write registers.\n'
registerExecuteCallbacksCode = '// Execute callbacks on registers.\n'
registerSetStageCode = '// Set pipeline stage for registers.\n'
registerUnsetStageCode = '// Unset pipeline stage for registers.\n'
registerClockCycleCode = '// Propagate pipeline stage for registers.\n'
registerStallCode = '// Stall pipeline for registers.\n'
registerAdvanceCode = '// Advance pipeline for registers.\n'
registerFlushCode = '// Flush registers.\n'
registerPrintCode = 'os << std::hex << std::showbase;\n\n// Print registers.\n'
for reg in self.regs:
if reg.constValue == None:
registerResetCode += reg.name.lower() + '.reset();\n'
registerWriteCode += 'ret = ret && ' + reg.name.lower(
) + '.write(data);\n'
registerWriteDbgCode += 'ret = ret && ' + reg.name.lower(
) + '.write_dbg(data);\n'
registerWriteForceCode += 'ret = ret && ' + reg.name.lower(
) + '.write_force(data);\n'
registerExecuteCallbacksCode += reg.name.lower(
) + '.execute_callbacks(type, 0, sizeof(' + registerMaxBitwidth.name.lower(
) + '));\n'
registerSetStageCode += reg.name.lower(
) + '.get_strategy()->set_stage(stage);\n'
registerUnsetStageCode += reg.name.lower(
) + '.get_strategy()->unset_stage();\n'
registerClockCycleCode += reg.name.lower() + '.clock_cycle();\n'
registerStallCode += reg.name.lower() + '.stall(stage);\n'
registerAdvanceCode += reg.name.lower() + '.advance();\n'
registerFlushCode += reg.name.lower() + '.flush(stage);\n'
registerPrintCode += 'os << ' + reg.name.lower(
) + '.name() << ": " << ' + reg.name.lower(
) + '.read_dbg() << \'\\n\';\n'
# Method Bodies: Register Banks
registerResetCode += '\n// Reset register banks.\n'
registerWriteCode += '\n// Write register banks.\n'
registerWriteDbgCode += '\n// Write register banks.\n'
registerWriteForceCode += '\n// Write register banks.\n'
registerExecuteCallbacksCode += '\n// Execute callbacks on register banks.\n'
registerSetStageCode += '\n// Set pipeline stage for register banks.\n'
registerUnsetStageCode += '\n// Unset pipeline stage for register banks.\n'
registerClockCycleCode += '// Propagate pipeline stage for register banks.\n'
registerStallCode += '// Stall pipeline for register banks.\n'
registerAdvanceCode += '// Advance pipeline for register banks.\n'
registerFlushCode += '// Flush register banks.\n'
registerPrintCode += '\n// Print register banks.\n'
for regBank in self.regBanks:
registerResetCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerResetCode += regBank.name.lower() + '[i].reset();\n'
registerResetCode += '}\n\n'
registerWriteCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerWriteCode += 'ret = ret && ' + regBank.name.lower(
) + '[i].write(data);\n'
registerWriteCode += '}\n\n'
registerWriteDbgCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerWriteDbgCode += 'ret = ret && ' + regBank.name.lower(
) + '[i].write_dbg(data);\n'
registerWriteDbgCode += '}\n\n'
registerWriteForceCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerWriteForceCode += 'ret = ret && ' + regBank.name.lower(
) + '[i].write_force(data);\n'
registerWriteForceCode += '}\n\n'
registerExecuteCallbacksCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerExecuteCallbacksCode += regBank.name.lower(
) + '[i].execute_callbacks(type, 0, sizeof(' + registerMaxBitwidth.name.lower(
) + '));\n'
registerExecuteCallbacksCode += '}\n\n'
registerSetStageCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerSetStageCode += regBank.name.lower(
) + '[i].set_stage(stage);\n'
registerSetStageCode += '}\n\n'
registerUnsetStageCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerUnsetStageCode += regBank.name.lower() + '[i].unset_stage();\n'
registerUnsetStageCode += '}\n\n'
registerClockCycleCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerClockCycleCode += regBank.name.lower() + '[i].clock_cycle();\n'
registerClockCycleCode += '}\n\n'
registerStallCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerStallCode += regBank.name.lower() + '[i].stall(stage);\n'
registerStallCode += '}\n\n'
registerAdvanceCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerAdvanceCode += regBank.name.lower() + '[i].advance();\n'
registerAdvanceCode += '}\n\n'
registerFlushCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerFlushCode += regBank.name.lower() + '[i].flush(stage);\n'
registerFlushCode += '}\n\n'
registerPrintCode += 'for (int i = 0; i < ' + str(
regBank.numRegs) + '; ++i) {\n'
registerPrintCode += 'os << ' + regBank.name.lower(
) + '[i].name() << ": " << ' + regBank.name.lower(
) + '[i].read_dbg() << \'\\n\';\n'
registerPrintCode += '}\n\n'
registerWriteCode += 'return ret;\n'
registerWriteDbgCode += 'return ret;\n'
registerWriteForceCode += 'return ret;\n'
registerPrintCode += 'os << std::dec;\nreturn os;\n'
# Method Declarations
registerResetMethod = cxx_writer.Method('reset',
cxx_writer.Code(registerResetCode),
cxx_writer.voidType, 'public')
registerMembers.append(registerResetMethod)
registerWriteDataParam = cxx_writer.Parameter(
'data',
registerMaxBitwidth.makeConst().makeRef())
registerWriteMethod = cxx_writer.Method('write',
cxx_writer.Code(registerWriteCode),
cxx_writer.boolType, 'public',
[registerWriteDataParam])
registerMembers.append(registerWriteMethod)
registerWriteDbgMethod = cxx_writer.Method(
'write_dbg', cxx_writer.Code(registerWriteDbgCode),
cxx_writer.boolType, 'public', [registerWriteDataParam])
registerMembers.append(registerWriteDbgMethod)
registerWriteForceMethod = cxx_writer.Method(
'write_force', cxx_writer.Code(registerWriteForceCode),
cxx_writer.boolType, 'public', [registerWriteDataParam])
registerMembers.append(registerWriteForceMethod)
registerExecuteCallbacksUint32RefType = cxx_writer.Type(
'uint32_t', const=True).makeRef()
registerExecuteCallbacksMethod = cxx_writer.Method(
'execute_callbacks', cxx_writer.Code(registerExecuteCallbacksCode),
cxx_writer.voidType, 'public', [
cxx_writer.Parameter(
'type',
cxx_writer.Type('scireg_ns::scireg_callback_type',
const=True).makeRef()),
cxx_writer.Parameter('offset',
registerExecuteCallbacksUint32RefType,
initValue='0'),
cxx_writer.Parameter('size',
cxx_writer.Type('uint32_t',
const=True).makeRef(),
initValue='0')
])
registerMembers.append(registerExecuteCallbacksMethod)
registerSetStageMethod = cxx_writer.Method(
'set_stage', cxx_writer.Code(registerSetStageCode),
cxx_writer.voidType, 'public',
[cxx_writer.Parameter('stage', cxx_writer.uintType)])
registerMembers.append(registerSetStageMethod)
registerUnsetStageMethod = cxx_writer.Method(
'unset_stage', cxx_writer.Code(registerUnsetStageCode),
cxx_writer.voidType, 'public')
registerMembers.append(registerUnsetStageMethod)
registerClockCycleMethod = cxx_writer.Method(
'clock_cycle', cxx_writer.Code(registerClockCycleCode),
cxx_writer.voidType, 'public')
registerMembers.append(registerClockCycleMethod)
registerStallMethod = cxx_writer.Method(
'stall', cxx_writer.Code(registerStallCode), cxx_writer.voidType,
'public', [cxx_writer.Parameter('stage', cxx_writer.uintType)])
registerMembers.append(registerStallMethod)
registerAdvanceMethod = cxx_writer.Method(
'advance', cxx_writer.Code(registerAdvanceCode), cxx_writer.voidType,
'public')
registerMembers.append(registerAdvanceMethod)
registerFlushMethod = cxx_writer.Method(
'flush', cxx_writer.Code(registerFlushCode), cxx_writer.voidType,
'public', [cxx_writer.Parameter('stage', cxx_writer.uintType)])
registerMembers.append(registerFlushMethod)
registerPrintOstreamRefType = cxx_writer.Type('std::ostream',
'iostream').makeRef()
registerPrintMethod = cxx_writer.MemberOperator(
'<<',
cxx_writer.Code(registerPrintCode),
registerPrintOstreamRefType,
'public', [cxx_writer.Parameter('os', registerPrintOstreamRefType)],
const=True)
registerMembers.append(registerPrintMethod)
## @} Methods
#---------------------------------------------------------------------------
registerClass = cxx_writer.ClassDeclaration('Registers',
registerMembers,
namespaces=[namespace])
registerClass.addDocString(
brief='Register Container Class',
detail=
'Contains all registers and register banks of the processor as member variables. It serves for encapsulating the instantiation details (defining fields, etc) away from the processor. It also simplifies passing the registers to the instructions, instead of passing each register individually.'
)
registerClass.addConstructor(registerCtor)
return [registerClass] + registerElements
# Opus/UrbanSim urban simulation software.
# Copyright (C) 2005-2009 University of Washington
# See opus_core/LICENSE
import os, time
import networkx as NX
from opus_core.storage_factory import StorageFactory
from opus_core.datasets.dataset import Dataset
print "Program started at %s" % time.asctime()
fh = open("C:/bhylee/GIS/Transit/IATBR06/03Network/psrc_edges_num.edgelist"
) # <<<< INPUT EDGELIST FILE
G = NX.read_edgelist(fh, create_using=NX.XDiGraph(), edgetype=int)
print "Done reading edgelist at %s" % time.asctime()
input_file = "C:/bhylee/GIS/Transit/IATBR06/03Network/psrc_o_d.txt" # <<<< INPUT ORIGIN/DESTINATION FILE
input_file_dir, input_file_name = os.path.split(input_file)
in_fh = open(os.path.join(input_file_dir, input_file_name), 'r')
#output
output_file = "results.tab"
out_fh = open(os.path.join(input_file_dir, output_file), 'w')
out_fh.write("orig\tdest\ttime\n")
#storage = StorageFactory().get_storage('tab_storage', subdir='store',
# storage_location=input_file_dir)
#dataset = Dataset(in_storage = storage, id_name = ['orig','dest'], in_table_name = input_file_name)
#origs = dataset.get_attribute("orig")
