def digital_out(): with nidaqmx.Task() as task: task.do_channels.add_do_chan('Dev1/port0/line0') task.timing.cfg_samp_clk_timing( 100, sample_mode=nidaqmx.constants.AcquisitionType.FINITE, samps_per_chan=200) signal = [True, False] * 5 task.write(signal) task.start() while not task.is_task_done(): pass
def sample_clock(): with nidaqmx.Task() as task: task.co_channels.add_co_pulse_chan_freq( 'Dev1/ctr1', freq=100000.0, idle_state=nidaqmx.constants.Level.LOW, duty_cycle=0.5) task.timing.cfg_implicit_timing( sample_mode=nidaqmx.constants.AcquisitionType.CONTINUOUS) co = nidaqmx._task_modules.channels.co_channel.COChannel( task._handle, 'Dev1/ctr1') task.start() #print(ci.ci_count) time.sleep(3)
def trigger(): with nidaqmx.Task() as trig: with nidaqmx.Task() as task: trig.co_channels.add_co_pulse_chan_freq('Dev1/ctr2', freq=0.2) trig.timing.cfg_implicit_timing( sample_mode=nidaqmx.constants.AcquisitionType.CONTINUOUS) trig.start() task.do_channels.add_do_chan('Dev1/port0/line0') task.timing.cfg_samp_clk_timing( 1, sample_mode=nidaqmx.constants.AcquisitionType.FINITE, samps_per_chan=2) task.triggers.start_trigger.cfg_dig_edge_start_trig( '/Dev1/Ctr2InternalOutput') task.write([True, False]) task.start() while not task.is_task_done(): pass
def zero_hyst(self): dt = 1E-3 N = 2000 f_oscill = 50 f_acq = 1 / dt tmax = N * dt omega = f_oscill * 2 * np.pi t = np.linspace(0, tmax, N) Vlist = np.cos(t * omega) * (tmax - t) / tmax * 5 with nidaqmx.Task() as task: source = self.source_menu.currentIndex() task.ao_channels.add_ao_voltage_chan('Dev1/ao' + str(source)) task.timing.cfg_samp_clk_timing( f_acq, sample_mode=nidaqmx.constants.AcquisitionType.FINITE, samps_per_chan=N) task.write(Vlist) task.start() while not task.is_task_done(): pass
def test_sample_clock(): with nidaqmx.Task() as task: task.do_channels.add_do_chan('Dev1/port2/line4') task.write(True) task.start()