def timings():
yield uut.a.eq(0x3)
yield Delay(1 * muS)
yield uut.a.eq(0x4)
yield Delay(1 * muS)
yield uut.a.eq(0x5)
yield Delay(1 * muS)
yield uut.a.eq(0x7)
yield Delay(1 * muS)
def timings():
yield adder.x.eq(0x00)
yield adder.y.eq(0x00)
yield Delay(muS)
yield adder.x.eq(0xFF)
yield adder.y.eq(0xFF)
yield Delay(muS)
yield adder.x.eq(0x00)
yield Delay(muS)
def process():
yield self.dut.data_input.eq(input)
yield Delay(1e-6)
yield self.dut.start.eq(1)
yield Delay(1e-6)
yield self.dut.start.eq(0)
#Delay for 16 clock cycles
for i in range(16):
yield Delay(1e-6)
self.assertEqual((yield self.dut.done), 1)
self.assertEqual((yield self.dut.success), 1)
self.assertEqual((yield self.dut.data_output), output)
def process(): # This design consist purely of combinational logic # so we just loop through all possible input values for i in range(256): yield m.data.eq(i) yield Delay(1e-6) yield Settle()
def process():
yield from self.toggle(self.shifter.r_next)
for n in range(self.num_rounds):
yield from self.shift_line(n)
yield from self.toggle(
self.shifter.r_next) # Throw away one word
yield Delay(100)
def process():
# Stochastic testing
for _ in range(300):
yield from verify(random.randint(0, 255), random.randint(0, 1),
random.randint(0, 31), random.randint(0, 1),
random.randint(0, 255), random.randint(0, 255),
random.randint(0, 31), random.randint(1, 2))
yield Delay(1e-6)
yield Settle()
def testbench_process():
#Run simulation for input word '101'
yield data_input.eq(0b0101)
yield start.eq(1)
yield Delay(1e-6)
yield start.eq(0)
#Delay for 10 clock cycles
for i in range(6):
yield Delay(1e-6)
#Run simulation for input word '110'
yield data_input.eq(0b1100)
yield start.eq(1)
yield Delay(1e-6)
yield start.eq(0)
#Delay for 10 clock cycles
for i in range(6):
yield Delay(1e-6)
def process():
nonlocal num_checks
for op in isa.AluOp:
yield alu.op.eq(op)
for a in blip.gen_fixtures(32, 24, 2):
yield alu.a.eq(a)
for b in blip.gen_fixtures(32, 12, 2):
if op == isa.AluOp.DIV and b == 0: continue
yield alu.b.eq(b)
yield Delay(1e-9)
ref_out, ref_ext, ref_flags = isa.emu.eval_alu(op, a, b)
out = yield alu.out
assert out == ref_out
num_checks += 1
def process():
# Stochastic testing, currently doesnt work for when it is shifted by 1 symbol
#yield from verify(random.randint(0, 255), random.randint(0, 1), random.randint(0, 31), random.randint(0, 1),
#random.randint(0, 255), random.randint(0, 255), random.randint(0, 31), random.randint(1, 2), random.randint(0, 1), 1, 1)
#yield from verify(random.randint(0, 255), random.randint(0, 1), random.randint(0, 31), random.randint(0, 1),
#random.randint(0, 255), random.randint(0, 255), random.randint(0, 31), random.randint(1, 2), random.randint(0, 1), 1, 1)
for _ in range(300):
yield from verify(random.randint(0, 255), random.randint(0, 1),
random.randint(0, 31), random.randint(0, 1),
random.randint(0, 255), random.randint(0, 255),
random.randint(0, 31), random.randint(1, 2),
random.randint(0, 1), 0, 0)
yield Delay(1e-6)
yield Settle()
def process():
# Initial state
yield m.spi_sclk.eq(1) # Clock starts high
yield m.spi_ssel.eq(1) # Not selected
yield m.spi_miso.eq(0) # Input data is low
yield m.data_out.eq(0xFF) # Data to be transmitted
yield Delay(1e-6) # 1 uS delay
for test_data in [0b11110000, 0b10101010, 0b00001111]:
# Simulate start of transaction
yield m.spi_ssel.eq(0) # Selected
yield Delay(1e-6) # 1 uS delay
# Simulate transaction
for bit in range(8):
yield m.spi_sclk.eq(0) # Falling edge of SPI clock
yield m.spi_mosi.eq((test_data >> (7 - bit)) & 1)
yield Delay(1e-6) # 1 uS delay
yield m.spi_sclk.eq(1) # Rising edge of SPI clock
yield Delay(1e-6) # 1 uS delay
# Simulate end of transaction
yield m.spi_ssel.eq(1) # Not selected
yield Delay(1e-6) # 1 uS delay
def data_proc():
sample_mask = 2**sample_width - 1
for i in range(10):
left = (3 * i) & sample_mask
right = (5 * i - 8) & sample_mask
yield design.left_in.i_valid.eq(True)
yield design.right_in.i_valid.eq(True)
yield design.left_in.i_data.eq(left)
yield design.right_in.i_data.eq(right)
yield Delay(1e-6)
valid = yield design.stereo_out.o_valid
assert valid
expected = ((left & sample_mask)
| ((right & sample_mask) << sample_width))
actual = yield design.stereo_out.o_data
assert actual == expected
def simulate():
from nmigen.back.pysim import Simulator, Delay, Settle
uart_baud = 9600
sim_clock_freq = uart_baud * 32
m = Module()
uart_tx = Signal()
uart_rx = Signal()
m.submodules.uart_high_speed = uart_high_speed = LowHighSpeedLoopback(
divisor=int(sim_clock_freq / uart_baud))
m.d.comb += uart_tx.eq(uart_high_speed.uart_tx)
m.d.comb += uart_high_speed.uart_rx.eq(uart_rx)
sim = Simulator(m)
sim.add_clock(1 / sim_clock_freq, domain="sync")
uart_tick = Delay(1 / uart_baud)
def process():
rx = uart_rx
yield rx.eq(1)
yield uart_tick
for i in range(4):
# start bit
yield rx.eq(0)
yield uart_tick
# 8 data bits
for i in range(1, 9):
yield rx.eq(i % 2 == 1)
yield uart_tick
# one stop bit
yield rx.eq(1)
yield uart_tick
# pause
for i in range(30):
yield uart_tick
sim.add_process(process) # or sim.add_sync_process(process), see below
# with sim.write_vcd("test.vcd", "test.gtkw", traces=[uart_tx, uart_rx]):
with sim.write_vcd("test.vcd", "test.gtkw",
traces=uart_high_speed.ports()):
sim.run()
def testbench_process():
#Run simulation for input word '010101111' (0 bit error)
yield data_input.eq(0b010101111)
yield Delay(1e-6)
yield start.eq(1)
yield Delay(1e-6)
yield start.eq(0)
#Delay for 25 clock cycles
for i in range(25):
yield Delay(1e-6)
#Run simulation for input word '010111111' (1 bit error)
yield data_input.eq(0b010111111)
yield Delay(1e-6)
yield start.eq(1)
yield Delay(1e-6)
yield start.eq(0)
#Delay for 25 clock cycles
for i in range(25):
yield Delay(1e-6)
#Run simulation for input word '110111111' (2 bit error)
yield data_input.eq(0b110111111)
yield Delay(1e-6)
yield start.eq(1)
yield Delay(1e-6)
yield start.eq(0)
#Delay for 25 clock cycles
for i in range(25):
yield Delay(1e-6)
#Run simulation for input word '011011011' (0 bit error)
yield data_input.eq(0b011011011)
yield Delay(1e-6)
yield start.eq(1)
yield Delay(1e-6)
yield start.eq(0)
#Delay for 25 clock cycles
for i in range(25):
yield Delay(1e-6)
def process():
for i in range(16):
yield seg.val.eq(i)
yield Delay()
result = yield seg.leds
print_leds(result)
def process():
# To be defined
yield Delay(100e-3)
def timings():
yield adder.x.eq(0x1)
yield adder.y.eq(0x2)
yield Delay(1 * muS)