def test_layout_10_wo(self):
elem = Element(10, "w")
self.assertEqual(elem.width, 10)
self.assertEqual(elem.access, Element.Access.W)
self.assertEqual(elem.layout, Layout.cast([
("w_data", 10),
("w_stb", 1),
]))
def test_layout_1_ro(self):
elem = Element(1, "r")
self.assertEqual(elem.width, 1)
self.assertEqual(elem.access, Element.Access.R)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 1),
("r_stb", 1),
]))
def test_layout_0_rw(self): # degenerate but legal case
elem = Element(0, access=Element.Access.RW)
self.assertEqual(elem.width, 0)
self.assertEqual(elem.access, Element.Access.RW)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 0),
("r_stb", 1),
("w_data", 0),
("w_stb", 1),
]))
def test_layout_8_rw(self):
elem = Element(8, access="rw")
self.assertEqual(elem.width, 8)
self.assertEqual(elem.access, Element.Access.RW)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 8),
("r_stb", 1),
("w_data", 8),
("w_stb", 1),
]))
def test_layout(self):
iface = Interface(addr_width=12, data_width=8)
self.assertEqual(iface.addr_width, 12)
self.assertEqual(iface.data_width, 8)
self.assertEqual(iface.layout, Layout.cast([
("addr", 12),
("r_data", 8),
("r_stb", 1),
("w_data", 8),
("w_stb", 1),
]))
def new(cls, dswol, *, flags=0):
"""
Create a PipeSpec.
The first arg is either the width of the data signal, the `Shape`
of the data signal, a `Layout` describing the data signal, or
a tuple of tuples that nMigen can coerce into a `Layout`.
The flags arg may include DATA_SIZE or START_STOP flags.
"""
# dsol: data shape or layout
# dwsol: data width, shape, or layout
if isinstance(dswol, (Shape, int)):
dsol = Shape.cast(dswol)
else:
dsol = Layout.cast(dswol)
return cls(flags, dsol)