def _cpu_reset(dut): """ The CPU reset value will be set and reset. The corresponding signal will be observed. """ access = RegAccess(dut) yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS, word_width=16, regaddr=DiPacket.SCM_REG.SYSRST.value, value=2) if dut.cpu_rst != 1: raise TestFailure("CPU reset signal could not be set!") yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS, word_width=16, regaddr=DiPacket.SCM_REG.SYSRST.value, value=0) if dut.cpu_rst != 0: raise TestFailure("CPU reset signal could not be reset!")
def test_dem_uart_activation(dut): """ Check if DEM_UART is handling the activation bit correctly """ access = RegAccess(dut) yield _init_dut(dut) dut._log.info("Check contents of MOD_CS") yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS, DiPacket.BASE_REG.MOD_CS.value, 16, 0) yield _activate_module(dut) dut._log.info("Check contents of MOD_CS") yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS, DiPacket.BASE_REG.MOD_CS.value, 16, 1) _bus_to_di_fifo.clear() write_thread = cocotb.fork(_bus_to_di_tx(dut, num_transfers=5)) read_thread = cocotb.fork(_bus_to_di_rx(dut, num_transfers=5)) yield read_thread.join() yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS, word_width=16, regaddr=DiPacket.BASE_REG.MOD_CS.value, value=0) write_thread = cocotb.fork(_bus_to_di_tx(dut, num_transfers=5)) # Wait one cycle to make sure the reader below doesn't accidentally try to # receive parts of the RegAccess response packet yield RisingEdge(dut.clk) # Don't confuse users of this test when they see a warning message dut._log.warning("The following warning 'packet receive timed out' is expected:") packet = yield NocDiReader(dut, dut.clk).receive_packet(set_ready=True) if packet: raise TestFailure("Received packet while module was deactivated") yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS, word_width=16, regaddr=DiPacket.BASE_REG.MOD_CS.value, value=1) read_thread = cocotb.fork(_bus_to_di_rx(dut, num_transfers=5)) yield read_thread.join()
def _activate_module(dut): access = RegAccess(dut) yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS, word_width=16, regaddr=DiPacket.BASE_REG.MOD_CS.value, value=1)
def _activate_module(dut): """ Set the MOD_CS_ACTIVE bit in the Control and Status register to 1 to enable emitting debug event packets. """ access = RegAccess(dut) yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS, word_width=16, regaddr=DiPacket.BASE_REG.MOD_CS.value, value=1)
def test_access_ext_registers(dut): """ Check if access to external registers works properly """ global _max_reg_size, _write_value, _req_addr, _req_width, _req_write access = RegAccess(dut) yield _init_dut(dut) # start thread that works as debug module debug_module = cocotb.fork(_debug_module_dummy(dut)) # different register widths to test req_reg_width = [16, 32, 64, 128] dut._log.info("Run write/read test of external registers") # write and read 2000 random values to random external registers for _ in range(200): # addresses 0x0 - 0x1ff are handled internally. Test adresses 0x200 - 0xffff _req_addr = random.randint(2**9, 2**16 - 1) _req_width = req_reg_width[random.randint(0, 3)] # ensure required width is not larger than MAX_REG_SIZE _req_width = _req_width if _req_width <= _max_reg_size else _max_reg_size _write_value = random.randint(0, 2**_req_width - 1) _req_write = True # write to register yield access.write_register(dest=MODULE_DI_ADDRESS, src=SENDER_DI_ADDRESS, word_width=_req_width, regaddr=_req_addr, value=_write_value) # wait a short random time wait = random.randint(0, 10) for _ in range(wait): yield RisingEdge(dut.clk) _req_write = False # check if value was correctly written to debug module yield access.assert_reg_value(MODULE_DI_ADDRESS, SENDER_DI_ADDRESS, _req_addr, _req_width, _write_value)