def __init__(self, clock):
from ovhw.cmdproc import CmdProc
self.submodules.tr = FTDI_randtest()
class ff:
def __getattr__(self, attrname):
if not attrname in self.__dict__:
self.__dict__[attrname] = ff()
return self.__dict__[attrname]
self.ff = ff()
self.ff.incoming_fifo.re = Signal()
self.ff.incoming_fifo.readable = Signal(reset=0)
self.ff.incoming_fifo.dout = Signal(8)
#self.sync += self.ff.incoming_fifo.readable.eq(0)
#self.sync += self.ff.incoming_fifo.dout.eq(0)
self.ff.output_fifo.we = Signal()
self.ff.output_fifo.writable = Signal(reset=1)
self.ff.output_fifo.din = Signal(8)
self.submodules.cm = CmdProc(self.ff, [self.tr])
def __init__(self):
from ovhw.cmdproc import CmdProc
class ff:
def __getattr__(self, attrname):
if not attrname in self.__dict__:
self.__dict__[attrname] = ff()
return self.__dict__[attrname]
self.ff = ff()
self.ff.incoming_fifo.re = Signal()
self.ff.incoming_fifo.readable = Signal(reset=0)
self.ff.incoming_fifo.dout = Signal(8)
#self.sync += self.ff.incoming_fifo.readable.eq(0)
#self.sync += self.ff.incoming_fifo.dout.eq(0)
self.ff.output_fifo.we = Signal()
self.ff.output_fifo.writable = Signal(reset=1)
self.ff.output_fifo.din = Signal(8)
self.submodules.dummy0 = DummySource(0xE0)
self.submodules.dummy1 = DummySource(0xE8)
self.submodules.cm = CmdProc(self.ff, [self.dummy0, self.dummy1])
def __init__(self, plat):
# Clocking
clk_ref = plat.request("clk12")
self.submodules.clockgen = clocking.ClockGen(clk_ref)
self.clock_domains.cd_sys = self.clockgen.cd_sys
# SDRAM Controller
sd_param = ovplatform.sdram_params.getSDRAMParams('mt48lc16m16a2')
self.submodules.sdramctl = SDRAMCTL(
plat.request("sdram"),
clk_out=self.clockgen.clk_sdram,
clk_sample=self.clockgen.clk_sdram_sample,
**sd_param._asdict()
)
# SDRAM Master arbiter
self.submodules.sdram_mux = SDRAMMux(self.sdramctl.hostif)
# SDRAM BIST
memsize = 2 ** (sd_param.colbits + sd_param.rowbits + sd_param.bankbits)
self.submodules.bist = SDRAMBIST(self.sdram_mux.getPort(), memsize)
self.submodules.sdram_test = SDRAMBISTCfg(self.bist)
# ULPI Interfce
# Diagnostics/Testing signals
ulpi_cd_rst = Signal()
ulpi_stp_ovr = Signal(1)
# ULPI physical layer
self.submodules.ulpi_pl = ULPI_pl(
plat.request("ulpi"), ulpi_cd_rst, ulpi_stp_ovr)
self.clock_domains.cd_ulpi = self.ulpi_pl.cd_ulpi
# ULPI controller
ulpi_reg = Record(ULPI_REG)
self.submodules.ulpi = RenameClockDomains(
ULPI_ctrl(self.ulpi_pl.ulpi_bus, ulpi_reg),
{"sys": "ulpi"}
)
# ULPI register R/W CSR interface
self.submodules.ucfg = ULPICfg(
self.cd_ulpi.clk, ulpi_cd_rst, self.ulpi_pl.ulpi_bus.rst,
ulpi_stp_ovr, ulpi_reg)
# Receive Path
self.submodules.ovf_insert = RenameClockDomains(
OverflowInserter(),
{"sys": "ulpi"}
)
self.submodules.udata_fifo = RenameClockDomains(
al_fifo.AsyncFIFO(ULPI_DATA_D, 1024),
{"write":"ulpi", "read":"sys"}
)
self.submodules.cfilt = RXCmdFilter()
self.submodules.cstream = Whacker(1024)
self.comb += [
self.ovf_insert.sink.connect(self.ulpi.data_out_source),
self.udata_fifo.sink.connect(self.ovf_insert.source),
self.cfilt.sink.connect(self.udata_fifo.source),
self.cstream.sink.connect(self.cfilt.source)
]
# FTDI bus interface
ftdi_io = plat.request("ftdi")
self.submodules.ftdi_bus = ftdi_bus = FTDI_sync245(self.clockgen.cd_sys.rst,
ftdi_io)
# FTDI command processor
self.submodules.randtest = FTDI_randtest()
self.submodules.cmdproc = CmdProc(self.ftdi_bus,
[self.randtest, self.cstream])
# GPIOs (leds/buttons)
self.submodules.leds = LED_outputs(plat.request('leds'),
[
[self.bist.busy, self.ftdi_bus.tx_ind],
[0, self.ftdi_bus.rx_ind],
[0]
], active=0)
self.submodules.buttons = BTN_status(~plat.request('btn'))
# Bind all device CSRs
self.csr_map = {
'leds': 0,
'buttons' : 1,
'ucfg' : 2,
'randtest' : 3,
'cstream' : 4,
'sdram_test' : 5,
}
self.submodules.csrbankarray = BankArray(self,
lambda name, _: self.csr_map[name])
# Connect FTDI CSR Master to CSR bus
self.submodules.incon = Interconnect(self.cmdproc.master, self.csrbankarray.get_buses())
def __init__(self, plat):
# Clocking
clk_ref = plat.request(
"clk12") # 12mhz reference clock from which all else is derived
self.submodules.clockgen = clocking.ClockGen(clk_ref)
self.clock_domains.cd_sys = self.clockgen.cd_sys
self.clock_domains.cd_pix1x = self.clockgen.cd_pix1x
self.clock_domains.cd_pix8x = self.clockgen.cd_pix8x
# SDRAM Controller
sd_param = ovplatform.sdram_params.getSDRAMParams('mt48lc16m16a2')
# Build the SDRAM controller (TODO: Replace with MISOC SDRAM controller)
self.submodules.sdramctl = SDRAMCTL(
plat.request("sdram"),
clk_out=self.clockgen.clk_sdram,
clk_sample=self.clockgen.clk_sdram_sample,
**sd_param._asdict())
# SDRAM Master arbiter (TODO: Replace with MISOC bus arbiter)
self.submodules.sdram_mux = SDRAMMux(self.sdramctl.hostif)
# SDRAM BIST (TODO: Rewrite to use internal bus)
memsize = 2**(sd_param.colbits + sd_param.rowbits + sd_param.bankbits)
self.submodules.bist = SDRAMBIST(self.sdram_mux.getPort(), memsize)
self.submodules.sdram_test = SDRAMBISTCfg(self.bist)
# SDRAM host read translator
self.submodules.sdram_host_read = SDRAM_Host_Read(
self.sdram_mux.getPort(), host_burst_length=0x20)
# SDRAM sink - sends data from USB capture to host
self.submodules.sdram_sink = SDRAM_Sink(self.sdram_mux.getPort())
# connect wptr/rptr for ringbuffer flow control
self.comb += self.sdram_host_read.wptr.eq(self.sdram_sink.wptr)
self.comb += self.sdram_sink.rptr.eq(self.sdram_host_read.rptr)
# ULPI Interfce
# Diagnostics/Testing signals
ulpi_cd_rst = Signal()
ulpi_stp_ovr = Signal(1)
# ULPI physical layer
self.submodules.ulpi_pl = ULPI_pl(plat.request("ulpi"), ulpi_cd_rst,
ulpi_stp_ovr)
self.clock_domains.cd_ulpi = self.ulpi_pl.cd_ulpi
# ULPI controller
ulpi_reg = Record(ULPI_REG)
self.submodules.ulpi = ClockDomainsRenamer({"sys": "ulpi"})(ULPI_ctrl(
self.ulpi_pl.ulpi_bus, ulpi_reg), )
# ULPI register R/W CSR interface
self.submodules.ucfg = ULPICfg(self.cd_ulpi.clk, ulpi_cd_rst,
self.ulpi_pl.ulpi_bus.rst, ulpi_stp_ovr,
ulpi_reg)
# Receive Path
self.submodules.ovf_insert = ClockDomainsRenamer({"sys": "ulpi"})(
OverflowInserter())
self.submodules.udata_fifo = ClockDomainsRenamer({
"write": "ulpi",
"read": "sys"
})(al_fifo.AsyncFIFO(ULPI_DATA_D, 1024))
self.submodules.cfilt = RXCmdFilter()
self.submodules.cstream = Whacker(1024)
self.comb += [
self.ulpi.data_out_source.connect(self.ovf_insert.sink),
self.ovf_insert.source.connect(self.udata_fifo.sink),
self.udata_fifo.source.connect(self.cfilt.sink),
self.cfilt.source.connect(self.cstream.sink),
# self.cstream.source.connect(self.sdram_sink.sink),
]
# FPD receiver
lvds_in = Cat(plat.request('spare', 0), plat.request('spare', 1))
debug = Cat(plat.request('spare', i) for i in range(2, 2 + 14))
self.submodules.fpdtop = FpdTop(lvds_in, debug)
self.comb += [
self.fpdtop.source.connect(self.sdram_sink.sink),
self.fpdtop.serdesstrobe.eq(self.clockgen.serdesstrobe)
]
# FTDI bus interface
ftdi_io = plat.request("ftdi")
self.submodules.ftdi_bus = ftdi_bus = FTDI_sync245(
self.clockgen.cd_sys.rst, ftdi_io)
# FTDI command processor
self.submodules.randtest = FTDI_randtest()
self.submodules.cmdproc = CmdProc(
self.ftdi_bus, [self.randtest, self.sdram_host_read])
# GPIOs (leds/buttons)
self.submodules.leds = LED_outputs(
plat.request('leds'),
[[self.bist.busy, self.ftdi_bus.tx_ind], [0, self.ftdi_bus.rx_ind],
[self.fpdtop.lock]],
active=0)
# Bind all device CSRs
self.csr_map = {
'leds': 0,
'buttons': 1,
'ucfg': 2,
'randtest': 3,
'cstream': 4,
'sdram_test': 5,
'sdram_host_read': 6,
'sdram_sink': 7,
'ovf_insert': 8,
'fpdtop': 9,
}
self.submodules.csrbankarray = CSRBankArray(
self, lambda name, _: self.csr_map[name])
# Connect FTDI CSR Master to CSR bus
self.submodules.incon = Interconnect(self.cmdproc.master,
self.csrbankarray.get_buses())