def test_get_vertices_from_vertex(self):
"""
test getting the vertex from a graph mapper via the vertex
"""
vertices = list()
vertices.append(SimpleMachineVertex(None, ""))
vertices.append(SimpleMachineVertex(None, ""))
vertex1 = SimpleMachineVertex(None, "")
vertex2 = SimpleMachineVertex(None, "")
edges = list()
edges.append(MachineEdge(vertices[0], vertices[1]))
edges.append(MachineEdge(vertices[1], vertices[1]))
graph_mapper = GraphMapper()
vert = SimpleTestVertex(4, "Some testing vertex")
vertex_slice = Slice(0, 1)
graph_mapper.add_vertex_mapping(vertex1, vertex_slice, vert)
vertex_slice = Slice(2, 3)
graph_mapper.add_vertex_mapping(vertex2, vertex_slice, vert)
returned_vertices = graph_mapper.get_machine_vertices(vert)
self.assertIn(vertex1, returned_vertices)
self.assertIn(vertex2, returned_vertices)
for v in vertices:
self.assertNotIn(v, returned_vertices)
def test_get_vertex_from_vertex(self):
"""
test that the graph mapper can retrieve a vertex from a given vertex
"""
vertices = list()
vertices.append(SimpleMachineVertex(None, ""))
vertices.append(SimpleMachineVertex(None, ""))
vertex1 = SimpleMachineVertex(None, "")
vertex2 = SimpleMachineVertex(None, "")
graph_mapper = GraphMapper()
vert = SimpleTestVertex(10, "Some testing vertex")
vertex_slice = Slice(0, 1)
graph_mapper.add_vertex_mapping(vertex1, vertex_slice, vert)
vertex_slice = Slice(2, 3)
graph_mapper.add_vertex_mapping(vertex2, vertex_slice, vert)
self.assertEqual(
vert, graph_mapper.get_application_vertex(vertex1))
self.assertEqual(
vert, graph_mapper.get_application_vertex(vertex2))
self.assertEqual(
None, graph_mapper.get_application_vertex(vertices[0]))
self.assertEqual(
None, graph_mapper.get_application_vertex(vertices[1]))
def test_get_vertex_from_vertex(self):
"""
test that the graph mapper can retrieve a vertex from a given vertex
"""
vertices = list()
vertices.append(SimpleMachineVertex(None, ""))
vertices.append(SimpleMachineVertex(None, ""))
vertex1 = SimpleMachineVertex(None, "")
vertex2 = SimpleMachineVertex(None, "")
graph_mapper = GraphMapper()
vert = SimpleTestVertex(10, "Some testing vertex")
vertex_slice = Slice(0, 1)
graph_mapper.add_vertex_mapping(vertex1, vertex_slice, vert)
vertex_slice = Slice(2, 3)
graph_mapper.add_vertex_mapping(vertex2, vertex_slice, vert)
self.assertEqual(
vert, graph_mapper.get_application_vertex(vertex1))
self.assertEqual(
vert, graph_mapper.get_application_vertex(vertex2))
self.assertEqual(
None, graph_mapper.get_application_vertex(vertices[0]))
self.assertEqual(
None, graph_mapper.get_application_vertex(vertices[1]))
def test_get_vertices_from_vertex(self):
"""
test getting the vertex from a graph mapper via the vertex
"""
vertices = list()
vertices.append(SimpleMachineVertex(None, ""))
vertices.append(SimpleMachineVertex(None, ""))
vertex1 = SimpleMachineVertex(None, "")
vertex2 = SimpleMachineVertex(None, "")
edges = list()
edges.append(MachineEdge(vertices[0], vertices[1]))
edges.append(MachineEdge(vertices[1], vertices[1]))
graph_mapper = GraphMapper()
vert = SimpleTestVertex(4, "Some testing vertex")
vertex_slice = Slice(0, 1)
graph_mapper.add_vertex_mapping(vertex1, vertex_slice, vert)
vertex_slice = Slice(2, 3)
graph_mapper.add_vertex_mapping(vertex2, vertex_slice, vert)
returned_vertices = graph_mapper.get_machine_vertices(vert)
self.assertIn(vertex1, returned_vertices)
self.assertIn(vertex2, returned_vertices)
for v in vertices:
self.assertNotIn(v, returned_vertices)
def test_with_application_vertices(self):
""" Test that an application vertex's data is rewritten correctly
"""
# Create a default SDRAM to set the max to default
SDRAM()
reload_region_data = [(0, [0] * 10), (1, [1] * 20)]
vertex = _TestApplicationVertex(10, reload_region_data)
m_slice_1 = Slice(0, 4)
m_slice_2 = Slice(5, 9)
m_vertex_1 = vertex.create_machine_vertex(m_slice_1, None, None, None)
m_vertex_2 = vertex.create_machine_vertex(m_slice_2, None, None, None)
graph_mapper = GraphMapper()
graph_mapper.add_vertex_mapping(m_vertex_1, m_slice_1, vertex)
graph_mapper.add_vertex_mapping(m_vertex_2, m_slice_2, vertex)
placements = Placements(
[Placement(m_vertex_1, 0, 0, 1),
Placement(m_vertex_2, 0, 0, 2)])
user_0_addresses = {
(placement.x, placement.y, placement.p): i * 1000
for i, placement in enumerate(placements.placements)
}
region_addresses = [i for i in range(MAX_MEM_REGIONS)]
transceiver = _MockTransceiver(user_0_addresses, region_addresses)
reloader = DSGRegionReloader()
reloader.__call__(transceiver, placements, "localhost", "test", False,
"test", graph_mapper)
regions_rewritten = transceiver.regions_rewritten
# Check that the number of times the data has been regenerated is
# correct
self.assertEqual(vertex.regenerate_call_count, placements.n_placements)
# Check that the number of regions rewritten is correct
self.assertEqual(len(transceiver.regions_rewritten),
placements.n_placements * len(reload_region_data))
# Check that the data rewritten is correct
for i, placement in enumerate(placements.placements):
user_0_address = user_0_addresses[placement.x, placement.y,
placement.p]
for j in range(len(reload_region_data)):
pos = (i * len(reload_region_data)) + j
region, data = reload_region_data[j]
address = get_region_base_address_offset(
user_0_address, 0) + region_addresses[region]
data = bytearray(numpy.array(data, dtype="uint32").tobytes())
# Check that the base address and data written is correct
self.assertEqual(regions_rewritten[pos], (address, data))
# Delete data files
shutil.rmtree("test")
def test_local_verts_go_to_local_lpgs_app_graph(self):
machine = VirtualMachine(width=12, height=12, with_wrap_arounds=True)
graph = MachineGraph("Test")
app_graph = ApplicationGraph("Test")
app_graph_mapper = GraphMapper()
default_params = {
'use_prefix': False,
'key_prefix': None,
'prefix_type': None,
'message_type': EIEIOType.KEY_32_BIT,
'right_shift': 0,
'payload_as_time_stamps': True,
'use_payload_prefix': True,
'payload_prefix': None,
'payload_right_shift': 0,
'number_of_packets_sent_per_time_step': 0,
'hostname': None,
'port': None,
'strip_sdp': None,
'board_address': None,
'tag': None}
# data stores needed by algorithm
live_packet_gatherers = dict()
extended = dict(default_params)
extended.update({'partition_id': "EVENTS"})
default_params_holder = LivePacketGatherParameters(**extended)
live_packet_gatherers[default_params_holder] = list()
live_packet_gatherers_to_vertex_mapping = defaultdict(dict)
placements = Placements()
# add LPG's (1 for each Ethernet connected chip
for chip in machine.ethernet_connected_chips:
vertex = LivePacketGather(**default_params)
app_graph.add_vertex(vertex)
vertex_slice = Slice(0, 0)
resources_required = vertex.get_resources_used_by_atoms(
vertex_slice)
mac_vertex = vertex.create_machine_vertex(
vertex_slice, resources_required)
graph.add_vertex(mac_vertex)
app_graph_mapper.add_vertex_mapping(
mac_vertex, Slice(0, 0), vertex)
placements.add_placement(
Placement(x=chip.x, y=chip.y, p=2, vertex=mac_vertex))
live_packet_gatherers_to_vertex_mapping[
default_params_holder][chip.x, chip.y] = mac_vertex
# tracker of wirings
verts_expected = defaultdict(list)
positions = list()
positions.append([0, 0, 0, 0])
positions.append([4, 4, 0, 0])
positions.append([1, 1, 0, 0])
positions.append([2, 2, 0, 0])
positions.append([8, 4, 8, 4])
positions.append([11, 4, 8, 4])
positions.append([4, 11, 4, 8])
positions.append([4, 8, 4, 8])
positions.append([0, 11, 8, 4])
positions.append([11, 11, 4, 8])
positions.append([8, 8, 4, 8])
positions.append([4, 0, 0, 0])
positions.append([7, 7, 0, 0])
# add graph vertices which reside on areas of the machine to ensure
# spread over boards.
for x, y, eth_x, eth_y in positions:
vertex = SimpleTestVertex(1)
app_graph.add_vertex(vertex)
vertex_slice = Slice(0, 0)
resources_required = vertex.get_resources_used_by_atoms(
vertex_slice)
mac_vertex = vertex.create_machine_vertex(
vertex_slice, resources_required)
graph.add_vertex(mac_vertex)
app_graph_mapper.add_vertex_mapping(
mac_vertex, vertex_slice, vertex)
live_packet_gatherers[default_params_holder].append(vertex)
verts_expected[eth_x, eth_y].append(mac_vertex)
placements.add_placement(
Placement(x=x, y=y, p=5, vertex=mac_vertex))
# run edge inserter that should go boom
edge_inserter = InsertEdgesToLivePacketGatherers()
edge_inserter(
live_packet_gatherer_parameters=live_packet_gatherers,
placements=placements,
live_packet_gatherers_to_vertex_mapping=(
live_packet_gatherers_to_vertex_mapping),
machine=machine, machine_graph=graph, application_graph=app_graph,
graph_mapper=app_graph_mapper)
# verify edges are in the right place
for chip in machine.ethernet_connected_chips:
edges = graph.get_edges_ending_at_vertex(
live_packet_gatherers_to_vertex_mapping[
default_params_holder][chip.x, chip.y])
for edge in edges:
self.assertIn(edge.pre_vertex, verts_expected[chip.x, chip.y])
# check app graph
for chip in machine.ethernet_connected_chips:
app_verts_expected = [
app_graph_mapper.get_application_vertex(vert)
for vert in verts_expected[chip.x, chip.y]]
lpg_machine = live_packet_gatherers_to_vertex_mapping[
default_params_holder][chip.x, chip.y]
lpg_app = app_graph_mapper.get_application_vertex(lpg_machine)
edges = app_graph.get_edges_ending_at_vertex(lpg_app)
for edge in edges:
self.assertIn(edge.pre_vertex, app_verts_expected)
def test_local_verts_go_to_local_lpgs_app_graph(self):
machine = VirtualMachine(width=12, height=12, with_wrap_arounds=True)
graph = MachineGraph("Test")
app_graph = ApplicationGraph("Test")
app_graph_mapper = GraphMapper()
default_params = {
'use_prefix': False,
'key_prefix': None,
'prefix_type': None,
'message_type': EIEIOType.KEY_32_BIT,
'right_shift': 0,
'payload_as_time_stamps': True,
'use_payload_prefix': True,
'payload_prefix': None,
'payload_right_shift': 0,
'number_of_packets_sent_per_time_step': 0,
'hostname': None,
'port': None,
'strip_sdp': None,
'board_address': None,
'tag': None,
'label': "test"
}
# data stores needed by algorithm
live_packet_gatherers = dict()
extended = dict(default_params)
extended.update({'partition_id': "EVENTS"})
default_params_holder = LivePacketGatherParameters(**extended)
live_packet_gatherers[default_params_holder] = list()
live_packet_gatherers_to_vertex_mapping = defaultdict(dict)
placements = Placements()
# add LPG's (1 for each Ethernet connected chip
for chip in machine.ethernet_connected_chips:
vertex = LivePacketGather(**default_params)
app_graph.add_vertex(vertex)
vertex_slice = Slice(0, 0)
resources_required = vertex.get_resources_used_by_atoms(
vertex_slice)
mac_vertex = vertex.create_machine_vertex(vertex_slice,
resources_required)
graph.add_vertex(mac_vertex)
app_graph_mapper.add_vertex_mapping(mac_vertex, Slice(0, 0),
vertex)
placements.add_placement(
Placement(x=chip.x, y=chip.y, p=2, vertex=mac_vertex))
live_packet_gatherers_to_vertex_mapping[default_params_holder][
chip.x, chip.y] = mac_vertex
# tracker of wirings
verts_expected = defaultdict(list)
positions = list()
positions.append([0, 0, 0, 0])
positions.append([4, 4, 0, 0])
positions.append([1, 1, 0, 0])
positions.append([2, 2, 0, 0])
positions.append([8, 4, 8, 4])
positions.append([11, 4, 8, 4])
positions.append([4, 11, 4, 8])
positions.append([4, 8, 4, 8])
positions.append([0, 11, 8, 4])
positions.append([11, 11, 4, 8])
positions.append([8, 8, 4, 8])
positions.append([4, 0, 0, 0])
positions.append([7, 7, 0, 0])
# add graph vertices which reside on areas of the machine to ensure
# spread over boards.
for x, y, eth_x, eth_y in positions:
vertex = TestVertex(1)
app_graph.add_vertex(vertex)
vertex_slice = Slice(0, 0)
resources_required = vertex.get_resources_used_by_atoms(
vertex_slice)
mac_vertex = vertex.create_machine_vertex(vertex_slice,
resources_required)
graph.add_vertex(mac_vertex)
app_graph_mapper.add_vertex_mapping(mac_vertex, vertex_slice,
vertex)
live_packet_gatherers[default_params_holder].append(vertex)
verts_expected[eth_x, eth_y].append(mac_vertex)
placements.add_placement(
Placement(x=x, y=y, p=5, vertex=mac_vertex))
# run edge inserter that should go boom
edge_inserter = InsertEdgesToLivePacketGatherers()
edge_inserter(live_packet_gatherer_parameters=live_packet_gatherers,
placements=placements,
live_packet_gatherers_to_vertex_mapping=(
live_packet_gatherers_to_vertex_mapping),
machine=machine,
machine_graph=graph,
application_graph=app_graph,
graph_mapper=app_graph_mapper)
# verify edges are in the right place
for chip in machine.ethernet_connected_chips:
edges = graph.get_edges_ending_at_vertex(
live_packet_gatherers_to_vertex_mapping[default_params_holder][
chip.x, chip.y])
for edge in edges:
self.assertIn(edge.pre_vertex, verts_expected[chip.x, chip.y])
# check app graph
for chip in machine.ethernet_connected_chips:
app_verts_expected = [
app_graph_mapper.get_application_vertex(vert)
for vert in verts_expected[chip.x, chip.y]
]
lpg_machine = live_packet_gatherers_to_vertex_mapping[
default_params_holder][chip.x, chip.y]
lpg_app = app_graph_mapper.get_application_vertex(lpg_machine)
edges = app_graph.get_edges_ending_at_vertex(lpg_app)
for edge in edges:
self.assertIn(edge.pre_vertex, app_verts_expected)
def test_write_synaptic_matrix_and_master_population_table(self):
MockSimulator.setup()
default_config_paths = os.path.join(
os.path.dirname(abstract_spinnaker_common.__file__),
AbstractSpiNNakerCommon.CONFIG_FILE_NAME)
config = conf_loader.load_config(
AbstractSpiNNakerCommon.CONFIG_FILE_NAME, default_config_paths)
config.set("Simulation", "one_to_one_connection_dtcm_max_bytes", 40)
machine_time_step = 1000.0
pre_app_vertex = SimpleApplicationVertex(10)
pre_vertex = SimpleMachineVertex(resources=None)
pre_vertex_slice = Slice(0, 9)
post_app_vertex = SimpleApplicationVertex(10)
post_vertex = SimpleMachineVertex(resources=None)
post_vertex_slice = Slice(0, 9)
post_slice_index = 0
one_to_one_connector_1 = OneToOneConnector(None)
one_to_one_connector_1.set_projection_information(
pre_app_vertex, post_app_vertex, None, machine_time_step)
one_to_one_connector_1.set_weights_and_delays(1.5, 1.0)
one_to_one_connector_2 = OneToOneConnector(None)
one_to_one_connector_2.set_projection_information(
pre_app_vertex, post_app_vertex, None, machine_time_step)
one_to_one_connector_2.set_weights_and_delays(2.5, 2.0)
all_to_all_connector = AllToAllConnector(None)
all_to_all_connector.set_projection_information(
pre_app_vertex, post_app_vertex, None, machine_time_step)
all_to_all_connector.set_weights_and_delays(4.5, 4.0)
direct_synapse_information_1 = SynapseInformation(
one_to_one_connector_1, SynapseDynamicsStatic(), 0)
direct_synapse_information_2 = SynapseInformation(
one_to_one_connector_2, SynapseDynamicsStatic(), 1)
all_to_all_synapse_information = SynapseInformation(
all_to_all_connector, SynapseDynamicsStatic(), 0)
app_edge = ProjectionApplicationEdge(pre_app_vertex, post_app_vertex,
direct_synapse_information_1)
app_edge.add_synapse_information(direct_synapse_information_2)
app_edge.add_synapse_information(all_to_all_synapse_information)
machine_edge = ProjectionMachineEdge(app_edge.synapse_information,
pre_vertex, post_vertex)
partition_name = "TestPartition"
graph = MachineGraph("Test")
graph.add_vertex(pre_vertex)
graph.add_vertex(post_vertex)
graph.add_edge(machine_edge, partition_name)
graph_mapper = GraphMapper()
graph_mapper.add_vertex_mapping(pre_vertex, pre_vertex_slice,
pre_app_vertex)
graph_mapper.add_vertex_mapping(post_vertex, post_vertex_slice,
post_app_vertex)
graph_mapper.add_edge_mapping(machine_edge, app_edge)
weight_scales = [4096.0, 4096.0]
key = 0
routing_info = RoutingInfo()
routing_info.add_partition_info(
PartitionRoutingInfo(
[BaseKeyAndMask(key, 0xFFFFFFF0)],
graph.get_outgoing_edge_partition_starting_at_vertex(
pre_vertex, partition_name)))
temp_spec = tempfile.mktemp()
spec_writer = FileDataWriter(temp_spec)
spec = DataSpecificationGenerator(spec_writer, None)
master_pop_sz = 1000
master_pop_region = 0
all_syn_block_sz = 2000
synapse_region = 1
spec.reserve_memory_region(master_pop_region, master_pop_sz)
spec.reserve_memory_region(synapse_region, all_syn_block_sz)
synapse_type = MockSynapseType()
synaptic_manager = SynapticManager(synapse_type=synapse_type,
ring_buffer_sigma=5.0,
spikes_per_second=100.0,
config=config)
synaptic_manager._write_synaptic_matrix_and_master_population_table(
spec, [post_vertex_slice], post_slice_index, post_vertex,
post_vertex_slice, all_syn_block_sz, weight_scales,
master_pop_region, synapse_region, routing_info, graph_mapper,
graph, machine_time_step)
spec.end_specification()
spec_writer.close()
spec_reader = FileDataReader(temp_spec)
executor = DataSpecificationExecutor(spec_reader,
master_pop_sz + all_syn_block_sz)
executor.execute()
master_pop_table = executor.get_region(0)
synaptic_matrix = executor.get_region(1)
all_data = bytearray()
all_data.extend(
master_pop_table.region_data[:master_pop_table.max_write_pointer])
all_data.extend(
synaptic_matrix.region_data[:synaptic_matrix.max_write_pointer])
master_pop_table_address = 0
synaptic_matrix_address = master_pop_table.max_write_pointer
direct_synapses_address = struct.unpack_from(
"<I", synaptic_matrix.region_data)[0]
direct_synapses_address += synaptic_matrix_address + 8
indirect_synapses_address = synaptic_matrix_address + 4
placement = Placement(None, 0, 0, 1)
transceiver = MockTransceiverRawData(all_data)
# Get the master population table details
items = synaptic_manager._poptable_type\
.extract_synaptic_matrix_data_location(
key, master_pop_table_address, transceiver,
placement.x, placement.y)
# The first entry should be direct, but the rest should be indirect;
# the second is potentially direct, but has been restricted by the
# restriction on the size of the direct matrix
assert len(items) == 3
# TODO: This has been changed because direct matrices are disabled!
assert not items[0][2]
assert not items[1][2]
assert not items[2][2]
data_1, row_len_1 = synaptic_manager._retrieve_synaptic_block(
transceiver=transceiver,
placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address,
key=key,
n_rows=pre_vertex_slice.n_atoms,
index=0,
using_extra_monitor_cores=False)
connections_1 = synaptic_manager._synapse_io.read_synapses(
direct_synapse_information_1, pre_vertex_slice, post_vertex_slice,
row_len_1, 0, 2, weight_scales, data_1, None,
app_edge.n_delay_stages, machine_time_step)
# The first matrix is a 1-1 matrix, so row length is 1
assert row_len_1 == 1
# Check that all the connections have the right weight and delay
assert len(connections_1) == post_vertex_slice.n_atoms
assert all([conn["weight"] == 1.5 for conn in connections_1])
assert all([conn["delay"] == 1.0 for conn in connections_1])
data_2, row_len_2 = synaptic_manager._retrieve_synaptic_block(
transceiver=transceiver,
placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address,
key=key,
n_rows=pre_vertex_slice.n_atoms,
index=1,
using_extra_monitor_cores=False)
connections_2 = synaptic_manager._synapse_io.read_synapses(
direct_synapse_information_2, pre_vertex_slice, post_vertex_slice,
row_len_2, 0, 2, weight_scales, data_2, None,
app_edge.n_delay_stages, machine_time_step)
# The second matrix is a 1-1 matrix, so row length is 1
assert row_len_2 == 1
# Check that all the connections have the right weight and delay
assert len(connections_2) == post_vertex_slice.n_atoms
assert all([conn["weight"] == 2.5 for conn in connections_2])
assert all([conn["delay"] == 2.0 for conn in connections_2])
data_3, row_len_3 = synaptic_manager._retrieve_synaptic_block(
transceiver=transceiver,
placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address,
key=key,
n_rows=pre_vertex_slice.n_atoms,
index=2,
using_extra_monitor_cores=False)
connections_3 = synaptic_manager._synapse_io.read_synapses(
all_to_all_synapse_information, pre_vertex_slice,
post_vertex_slice, row_len_3, 0, 2, weight_scales, data_3, None,
app_edge.n_delay_stages, machine_time_step)
# The third matrix is an all-to-all matrix, so length is n_atoms
assert row_len_3 == post_vertex_slice.n_atoms
# Check that all the connections have the right weight and delay
assert len(connections_3) == \
post_vertex_slice.n_atoms * pre_vertex_slice.n_atoms
assert all([conn["weight"] == 4.5 for conn in connections_3])
assert all([conn["delay"] == 4.0 for conn in connections_3])
def test_write_synaptic_matrix_and_master_population_table(self):
MockSimulator.setup()
# Add an sdram so maxsdram is high enough
SDRAM(10000)
default_config_paths = os.path.join(
os.path.dirname(abstract_spinnaker_common.__file__),
AbstractSpiNNakerCommon.CONFIG_FILE_NAME)
config = conf_loader.load_config(
AbstractSpiNNakerCommon.CONFIG_FILE_NAME, default_config_paths)
config.set("Simulation", "one_to_one_connection_dtcm_max_bytes", 40)
machine_time_step = 1000.0
pre_app_vertex = SimpleApplicationVertex(10)
pre_vertex = SimpleMachineVertex(resources=None)
pre_vertex_slice = Slice(0, 9)
post_app_vertex = SimpleApplicationVertex(10)
post_vertex = SimpleMachineVertex(resources=None)
post_vertex_slice = Slice(0, 9)
post_slice_index = 0
one_to_one_connector_1 = OneToOneConnector(None)
one_to_one_connector_1.set_projection_information(
pre_app_vertex, post_app_vertex, None, machine_time_step)
one_to_one_connector_2 = OneToOneConnector(None)
one_to_one_connector_2.set_projection_information(
pre_app_vertex, post_app_vertex, None, machine_time_step)
all_to_all_connector = AllToAllConnector(None)
all_to_all_connector.set_projection_information(
pre_app_vertex, post_app_vertex, None, machine_time_step)
direct_synapse_information_1 = SynapseInformation(
one_to_one_connector_1, SynapseDynamicsStatic(), 0, 1.5, 1.0)
direct_synapse_information_2 = SynapseInformation(
one_to_one_connector_2, SynapseDynamicsStatic(), 1, 2.5, 2.0)
all_to_all_synapse_information = SynapseInformation(
all_to_all_connector, SynapseDynamicsStatic(), 0, 4.5, 4.0)
app_edge = ProjectionApplicationEdge(
pre_app_vertex, post_app_vertex, direct_synapse_information_1)
app_edge.add_synapse_information(direct_synapse_information_2)
app_edge.add_synapse_information(all_to_all_synapse_information)
machine_edge = ProjectionMachineEdge(
app_edge.synapse_information, pre_vertex, post_vertex)
partition_name = "TestPartition"
graph = MachineGraph("Test")
graph.add_vertex(pre_vertex)
graph.add_vertex(post_vertex)
graph.add_edge(machine_edge, partition_name)
graph_mapper = GraphMapper()
graph_mapper.add_vertex_mapping(
pre_vertex, pre_vertex_slice, pre_app_vertex)
graph_mapper.add_vertex_mapping(
post_vertex, post_vertex_slice, post_app_vertex)
graph_mapper.add_edge_mapping(machine_edge, app_edge)
weight_scales = [4096.0, 4096.0]
key = 0
routing_info = RoutingInfo()
routing_info.add_partition_info(PartitionRoutingInfo(
[BaseKeyAndMask(key, 0xFFFFFFF0)],
graph.get_outgoing_edge_partition_starting_at_vertex(
pre_vertex, partition_name)))
temp_spec = tempfile.mktemp()
spec_writer = FileDataWriter(temp_spec)
spec = DataSpecificationGenerator(spec_writer, None)
master_pop_sz = 1000
master_pop_region = 0
all_syn_block_sz = 2000
synapse_region = 1
direct_region = 2
spec.reserve_memory_region(master_pop_region, master_pop_sz)
spec.reserve_memory_region(synapse_region, all_syn_block_sz)
synaptic_manager = SynapticManager(
n_synapse_types=2, ring_buffer_sigma=5.0,
spikes_per_second=100.0, config=config)
# UGLY but the mock transceiver NEED generate_on_machine be False
abstract_generate_connector_on_machine.IS_PYNN_8 = False
synaptic_manager._write_synaptic_matrix_and_master_population_table(
spec, [post_vertex_slice], post_slice_index, post_vertex,
post_vertex_slice, all_syn_block_sz, weight_scales,
master_pop_region, synapse_region, direct_region, routing_info,
graph_mapper, graph, machine_time_step)
spec.end_specification()
spec_writer.close()
spec_reader = FileDataReader(temp_spec)
executor = DataSpecificationExecutor(
spec_reader, master_pop_sz + all_syn_block_sz)
executor.execute()
master_pop_table = executor.get_region(0)
synaptic_matrix = executor.get_region(1)
direct_matrix = executor.get_region(2)
all_data = bytearray()
all_data.extend(master_pop_table.region_data[
:master_pop_table.max_write_pointer])
all_data.extend(synaptic_matrix.region_data[
:synaptic_matrix.max_write_pointer])
all_data.extend(direct_matrix.region_data[
:direct_matrix.max_write_pointer])
master_pop_table_address = 0
synaptic_matrix_address = master_pop_table.max_write_pointer
direct_synapses_address = (
synaptic_matrix_address + synaptic_matrix.max_write_pointer)
direct_synapses_address += 4
indirect_synapses_address = synaptic_matrix_address
placement = Placement(None, 0, 0, 1)
transceiver = MockTransceiverRawData(all_data)
# Get the master population table details
items = synaptic_manager._poptable_type\
.extract_synaptic_matrix_data_location(
key, master_pop_table_address, transceiver,
placement.x, placement.y)
# The first entry should be direct, but the rest should be indirect;
# the second is potentially direct, but has been restricted by the
# restriction on the size of the direct matrix
assert len(items) == 3
assert items[0][2]
assert not items[1][2]
assert not items[2][2]
data_1, row_len_1 = synaptic_manager._retrieve_synaptic_block(
transceiver=transceiver, placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address, key=key,
n_rows=pre_vertex_slice.n_atoms, index=0,
using_extra_monitor_cores=False)
connections_1 = synaptic_manager._synapse_io.read_synapses(
direct_synapse_information_1, pre_vertex_slice, post_vertex_slice,
row_len_1, 0, 2, weight_scales, data_1, None,
app_edge.n_delay_stages, machine_time_step)
# The first matrix is a 1-1 matrix, so row length is 1
assert row_len_1 == 1
# Check that all the connections have the right weight and delay
assert len(connections_1) == post_vertex_slice.n_atoms
assert all([conn["weight"] == 1.5 for conn in connections_1])
assert all([conn["delay"] == 1.0 for conn in connections_1])
data_2, row_len_2 = synaptic_manager._retrieve_synaptic_block(
transceiver=transceiver, placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address, key=key,
n_rows=pre_vertex_slice.n_atoms, index=1,
using_extra_monitor_cores=False)
connections_2 = synaptic_manager._synapse_io.read_synapses(
direct_synapse_information_2, pre_vertex_slice, post_vertex_slice,
row_len_2, 0, 2, weight_scales, data_2, None,
app_edge.n_delay_stages, machine_time_step)
# The second matrix is a 1-1 matrix, so row length is 1
assert row_len_2 == 1
# Check that all the connections have the right weight and delay
assert len(connections_2) == post_vertex_slice.n_atoms
assert all([conn["weight"] == 2.5 for conn in connections_2])
assert all([conn["delay"] == 2.0 for conn in connections_2])
data_3, row_len_3 = synaptic_manager._retrieve_synaptic_block(
transceiver=transceiver, placement=placement,
master_pop_table_address=master_pop_table_address,
indirect_synapses_address=indirect_synapses_address,
direct_synapses_address=direct_synapses_address, key=key,
n_rows=pre_vertex_slice.n_atoms, index=2,
using_extra_monitor_cores=False)
connections_3 = synaptic_manager._synapse_io.read_synapses(
all_to_all_synapse_information, pre_vertex_slice,
post_vertex_slice, row_len_3, 0, 2, weight_scales, data_3, None,
app_edge.n_delay_stages, machine_time_step)
# The third matrix is an all-to-all matrix, so length is n_atoms
assert row_len_3 == post_vertex_slice.n_atoms
# Check that all the connections have the right weight and delay
assert len(connections_3) == \
post_vertex_slice.n_atoms * pre_vertex_slice.n_atoms
assert all([conn["weight"] == 4.5 for conn in connections_3])
assert all([conn["delay"] == 4.0 for conn in connections_3])