def main_intel_x64(config, generator):
data_path = config.pal_data_dir
indir = os.path.join(data_path, "x86_64/register/control_register")
outdir = os.path.join(config.pal_output_dir, "control_register")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
indir = os.path.join(data_path, "x86_64/register/cpuid")
outdir = os.path.join(config.pal_output_dir, "cpuid")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
indir = os.path.join(data_path, "x86_64/register/msr")
outdir = os.path.join(config.pal_output_dir, "msr")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
indir = os.path.join(data_path, "x86_64/register/vmcs")
outdir = os.path.join(config.pal_output_dir, "vmcs")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
def run(self, generators):
input_root = self.config.pal_data_dir
output_root = self.config.pal_output_dir
for generator in generators:
indir = os.path.join(input_root, "armv8-a/register/aarch64")
outdir = os.path.join(ouput_root, "armv8-a/register/aarch64")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate_registers(copy.deepcopy(regs), outdir)
indir = os.path.join(input_root, "armv8-a/register/aarch32")
outdir = os.path.join(ouput_root, "armv8-a/register/aarch32")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate_registers(copy.deepcopy(regs), outdir)
def main_armv8a(config, generator):
data_path = config.pal_data_dir
if config.access_mechanism == "gas_aarch64" \
or config.access_mechanism == "test":
indir = os.path.join(data_path, "armv8-a/register/aarch64")
outdir = os.path.join(config.pal_output_dir, "aarch64")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
# Quirk: VMPIDR_EL2 and VPIDR_EL2 have mrc and mcr defined as primary
# access mechanisms (which aren't compilable with an aarch64 toolchain)
regs = transforms["remove_coprocessor_am"].transform(regs)
generator.generate(copy.deepcopy(regs), outdir)
if config.access_mechanism == "gas_aarch32" \
or config.access_mechanism == "test":
indir = os.path.join(data_path, "armv8-a/register/aarch32")
outdir = os.path.join(config.pal_output_dir, "aarch32")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
if config.access_mechanism == "yaml":
indir = os.path.join(data_path, "armv8-a/register/aarch64")
outdir = os.path.join(config.pal_output_dir, "aarch64")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
indir = os.path.join(data_path, "armv8-a/register/aarch32")
outdir = os.path.join(config.pal_output_dir, "aarch32")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
indir = os.path.join(data_path, "armv8-a/register/external")
outdir = os.path.join(config.pal_output_dir, "external")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
def run(self, generators):
input_root = self.config.pal_data_dir
output_root = self.config.pal_output_dir
for generator in generators:
indir = os.path.join(input_root, "x86_64/register/control_register")
outdir = os.path.join(output_root, "control_register")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate_registers(copy.deepcopy(regs), outdir)
indir = os.path.join(input_root, "x86_64/register/cpuid")
outdir = os.path.join(output_root, "cpuid")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate_registers(copy.deepcopy(regs), outdir)
indir = os.path.join(input_root, "x86_64/register/msr")
outdir = os.path.join(output_root, "msr")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate_registers(copy.deepcopy(regs), outdir)
indir = os.path.join(input_root, "x86_64/register/vmcs")
outdir = os.path.join(output_root, "vmcs")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate_registers(copy.deepcopy(regs), outdir)
indir = os.path.join(input_root, "x86_64/instruction/architectural")
outdir = os.path.join(output_root, "instruction")
os.makedirs(outdir, exist_ok=True)
instructions = parse_instructions(indir)
generator.generate_instructions(copy.deepcopy(instructions), outdir)
indir = os.path.join(input_root, "x86_64/instruction/logical")
outdir = os.path.join(output_root, "instruction")
os.makedirs(outdir, exist_ok=True)
instructions = parse_instructions(indir)
generator.generate_instructions(copy.deepcopy(instructions), outdir)
def main_acpi(config, generator):
data_path = config.pal_data_dir
from pal.logger import logger
acpi_top_dir = os.path.join(data_path, "acpi")
acpi_sub_dirs = next(os.walk(acpi_top_dir))[1]
for subdir in acpi_sub_dirs:
indir = os.path.join(acpi_top_dir, subdir)
outdir = os.path.join(config.pal_output_dir, "acpi", subdir)
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate(copy.deepcopy(regs), outdir)
def run(self, generators):
input_root = self.config.pal_data_dir
output_root = self.config.pal_output_dir
for generator in generators:
acpi_top_dir = os.path.join(input_root, "acpi")
acpi_sub_dirs = next(os.walk(acpi_top_dir))[1]
for subdir in acpi_sub_dirs:
indir = os.path.join(acpi_top_dir, subdir)
outdir = os.path.join(output_root, "acpi", subdir)
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
generator.generate_registers(copy.deepcopy(regs), outdir)
def run(self, generators):
input_root = self.config.pal_data_dir
output_root = self.config.pal_output_dir
for generator in generators:
indir = os.path.join(input_root, "armv8-a/register/aarch64")
outdir = os.path.join(output_root, "aarch64")
os.makedirs(outdir, exist_ok=True)
regs = parse_registers(indir)
# Quirk: VMPIDR_EL2 and VPIDR_EL2 have mrc and mcr defined as primary
# access mechanisms (which aren't compilable with an aarch64 toolchain)
regs = transforms["remove_coprocessor_am"].transform(regs)
generator.generate_registers(copy.deepcopy(regs), outdir)