def __init__(s, nports, src_msgs, sink_msgs, stall_prob, latency,
src_delay, sink_delay):
# Messge type
mem_msgs = MemMsg(32, 32)
# Instantiate models
s.srcs = []
for i in range(nports):
s.srcs.append(TestSource(mem_msgs.req, src_msgs[i], src_delay))
s.mem = TestMemory(mem_msgs, nports, stall_prob, latency)
s.sinks = []
for i in range(nports):
s.sinks.append(TestSink(mem_msgs.resp, sink_msgs[i], sink_delay))
# Connect
for i in range(nports):
s.connect(s.srcs[i].out, s.mem.reqs[i])
s.connect(s.sinks[i].in_, s.mem.resps[i])
def __init__( s ):
# interface
s.in_control = InValRdyBundle (inst_msg() ) # control word
s.in_neighbor = InValRdyBundle[2] (nWid)
s.out_fsm = OutValRdyBundle (1) # response to FSM
s.out_neighbor = OutValRdyBundle[2] (nWid)
s.ocmreqs = OutValRdyBundle (MemMsg(8,32,nWid))
s.ocmresps = InValRdyBundle (MempMsg(8, nWid))
# PE local register file
s.rf = RegisterFile( nWid, nReg, 2, 1 )
# temporary variables
s.src0_tmp = Wire( nWid )
s.src1_tmp = Wire( nWid )
s.des_tmp = Wire( nWid )
s.go = Wire( 1 )
def __init__(s, mem_ifc_types=MemMsg(32, 32)):
# Interface
s.xcelreq = InValRdyBundle(XcelReqMsg())
s.xcelresp = OutValRdyBundle(XcelRespMsg())
#s.memreq = InValRdyBundle ( mem_ifc_types.req )
#s.memresp = OutValRdyBundle ( mem_ifc_types.resp )
# Adapters
s.xcelreq_q = InValRdyQueueAdapter(s.xcelreq)
s.xcelresp_q = OutValRdyQueueAdapter(s.xcelresp)
# Accelerator registers
s.xregs = [Bits(32, 0) for _ in xrange(32)]
# Concurrent block
@s.tick_fl
def block():
# We loop forever handling accelerator requests.
while True:
xcelreq_msg = s.xcelreq_q.popleft()
if xcelreq_msg.type_ == XcelReqMsg.TYPE_READ:
data = s.xregs[xcelreq_msg.raddr]
s.xcelresp_q.append(XcelRespMsg().mk_rd(data))
else:
s.xregs[xcelreq_msg.raddr] = xcelreq_msg.data
s.xcelresp_q.append(XcelRespMsg().mk_wr())
def mreq(a):
return MemMsg(32, 32).req.mk_msg(0, a, 0, 0)
def __init__( s, reset_vector=0, test_en=True ):
s.reset_vector = reset_vector
s.test_en = test_en
# Proc/Mngr Interface
s.mngr2proc = InValRdyBundle( 32 )
s.proc2mngr = OutValRdyBundle( 32 )
# Instruction Memory Request/Response Interface
s.imemreq = OutValRdyBundle ( MemReqMsg(32,32) )
s.imemresp = InValRdyBundle ( MemRespMsg(32) )
# Data Memory Request/Response Interface
s.dmemreq = OutValRdyBundle ( MemReqMsg(32,32) )
s.dmemresp = InValRdyBundle ( MemRespMsg(32) )
# Accelerator Interface
s.xcelreq = OutValRdyBundle( XcelReqMsg() )
s.xcelresp = InValRdyBundle( XcelRespMsg() )
# Extra Interface
s.go = InPort ( 1 )
s.status = OutPort ( 32 )
s.stats_en = OutPort ( 1 )
s.num_insts = OutPort ( 32 )
# Queue Adapters
s.mngr2proc_q = InValRdyQueueAdapter ( s.mngr2proc )
s.proc2mngr_q = OutValRdyQueueAdapter ( s.proc2mngr )
s.imemreq_q = OutValRdyQueueAdapter ( s.imemreq )
s.imemresp_q = InValRdyQueueAdapter ( s.imemresp )
s.dmemreq_q = OutValRdyQueueAdapter ( s.dmemreq )
s.dmemresp_q = InValRdyQueueAdapter ( s.dmemresp )
s.xcelreq_q = OutValRdyQueueAdapter ( s.xcelreq )
s.xcelresp_q = InValRdyQueueAdapter ( s.xcelresp )
# Helpers to make memory read/write requests
mem_ifc_types = MemMsg(32,32)
s.mk_rd = mem_ifc_types.req.mk_rd
s.mk_wr = mem_ifc_types.req.mk_wr
# Pipeline queues
s.pc_queue_FX = Queue(4)
s.inst_queue_XW = Queue(4)
s.wb_queue_XW = Queue(4)
s.R = ParcProcCL.RegisterFile()
s.stall_X = False
s.stall_W = False
s.stall_type_X = " "
s.stall_type_W = " "
s.WB_NONE = 0
s.WB_REGWR = 1
s.ifetch_wait = 0
# Reset
s.reset_proc()
def __init__(s):
# Parameters
num_reqers = 4 # 4 processors
num_reqees = 4 # 4 data caches
num_ports = max(num_reqers, num_reqees) # We still have 4 ports
nopaque_nbits = 8
mopaque_nbits = 8
addr_nbits = 32
data_nbits = 32 # CacheNet only deals with 32 bit requests
# Interface
s.procifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.cacheifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.procreq = InValRdyBundle[num_ports](s.procifc.req)
s.procresp = OutValRdyBundle[num_ports](s.procifc.resp)
s.cachereq = OutValRdyBundle[num_ports](s.cacheifc.req)
s.cacheresp = InValRdyBundle[num_ports](s.cacheifc.resp)
# Connection
s.inner = CacheNetVRTL_inner()
procreq_nbits = s.procifc.req.nbits
procresp_nbits = s.procifc.resp.nbits
cachereq_nbits = s.cacheifc.req.nbits
cacheresp_nbits = s.cacheifc.resp.nbits
for i in xrange(num_ports):
s.connect_pairs(
s.procreq[i].val,
s.inner.procreq_val[i],
s.procreq[i].rdy,
s.inner.procreq_rdy[i],
s.procreq[i].msg,
s.inner.procreq_msg[i * procreq_nbits:(i + 1) * procreq_nbits],
s.procresp[i].val,
s.inner.procresp_val[i],
s.procresp[i].rdy,
s.inner.procresp_rdy[i],
s.procresp[i].msg,
s.inner.procresp_msg[i * procresp_nbits:(i + 1) *
procresp_nbits],
s.cachereq[i].val,
s.inner.cachereq_val[i],
s.cachereq[i].rdy,
s.inner.cachereq_rdy[i],
s.cachereq[i].msg,
s.inner.cachereq_msg[i * cachereq_nbits:(i + 1) *
cachereq_nbits],
s.cacheresp[i].val,
s.inner.cacheresp_val[i],
s.cacheresp[i].rdy,
s.inner.cacheresp_rdy[i],
s.cacheresp[i].msg,
s.inner.cacheresp_msg[i * cacheresp_nbits:(i + 1) *
cacheresp_nbits],
)
def __init__(s):
# Parameters
num_cores = 1
opaque_nbits = 8
addr_nbits = 32
icache_nbytes = 256
dcache_nbytes = 256
data_nbits = 32
cacheline_nbits = 128
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.memifc = MemMsg(opaque_nbits, addr_nbits, cacheline_nbits)
s.mngr2proc = InValRdyBundle(32)
s.proc2mngr = OutValRdyBundle(32)
s.imemreq = OutValRdyBundle(s.memifc.req)
s.imemresp = InValRdyBundle(s.memifc.resp)
s.dmemreq = OutValRdyBundle(s.memifc.req)
s.dmemresp = InValRdyBundle(s.memifc.resp)
# These ports are for statistics. Basically we want to provide the
# simulator with some useful signals to let the simulator calculate
# cache miss rate.
s.stats_en = OutPort(1)
s.commit_inst = OutPort(1)
s.icache_miss = OutPort(1)
s.icache_access = OutPort(1)
s.dcache_miss = OutPort(1)
s.dcache_access = OutPort(1)
#---------------------------------------------------------------------
# Verilog import
#---------------------------------------------------------------------
s.set_params({'dummy': 0})
# connect to Verilog module
s.set_ports({
'clk': s.clk,
'reset': s.reset,
'mngr2proc_msg': s.mngr2proc.msg,
'mngr2proc_val': s.mngr2proc.val,
'mngr2proc_rdy': s.mngr2proc.rdy,
'proc2mngr_msg': s.proc2mngr.msg,
'proc2mngr_val': s.proc2mngr.val,
'proc2mngr_rdy': s.proc2mngr.rdy,
'imemreq_msg': s.imemreq.msg,
'imemreq_val': s.imemreq.val,
'imemreq_rdy': s.imemreq.rdy,
'imemresp_msg': s.imemresp.msg,
'imemresp_val': s.imemresp.val,
'imemresp_rdy': s.imemresp.rdy,
'dmemreq_msg': s.dmemreq.msg,
'dmemreq_val': s.dmemreq.val,
'dmemreq_rdy': s.dmemreq.rdy,
'dmemresp_msg': s.dmemresp.msg,
'dmemresp_val': s.dmemresp.val,
'dmemresp_rdy': s.dmemresp.rdy,
'stats_en': s.stats_en,
'commit_inst': s.commit_inst,
'icache_miss': s.icache_miss,
'icache_access': s.icache_access,
'dcache_miss': s.dcache_miss,
'dcache_access': s.dcache_access,
})
def __init__(s,
mem_ifc_dtypes=MemMsg(32, 32),
nports=1,
stall_prob=0,
latency=0,
mem_nbytes=2**20):
# Interface
xr = range
s.reqs = [InValRdyBundle(mem_ifc_dtypes.req) for _ in xr(nports)]
s.resps = [OutValRdyBundle(mem_ifc_dtypes.resp) for _ in xr(nports)]
# Checks
assert mem_ifc_dtypes.req.data.nbits % 8 == 0
assert mem_ifc_dtypes.resp.data.nbits % 8 == 0
# Buffers to hold memory request/response messages
s.reqs_q = []
for req in s.reqs:
s.reqs_q.append(InValRdyRandStallAdapter(req, stall_prob))
s.resps_q = []
for resp in s.resps:
s.resps_q.append(OutValRdyInelasticPipeAdapter(resp, latency))
# Actual memory
s.mem = bytearray(mem_nbytes)
# Local constants
s.mem_ifc_dtypes = mem_ifc_dtypes
s.nports = nports
#---------------------------------------------------------------------
# Tick
#---------------------------------------------------------------------
@s.tick_cl
def tick():
# Tick adapters
for req_q, resp_q in zip(s.reqs_q, s.resps_q):
req_q.xtick()
resp_q.xtick()
# Iterate over input/output queues
for req_q, resp_q in zip(s.reqs_q, s.resps_q):
if not req_q.empty() and not resp_q.full():
# Dequeue memory request message
memreq = req_q.deq()
# When len is zero, then we use all of the data
nbytes = memreq.len
if memreq.len == 0:
nbytes = s.mem_ifc_dtypes.req.data.nbits / 8
# Handle a read request
if memreq.type_ == MemReqMsg.TYPE_READ:
# Copy the bytes from the bytearray into read data bits
read_data = Bits(s.mem_ifc_dtypes.req.data.nbits)
for j in range(nbytes):
read_data[j * 8:j * 8 + 8] = s.mem[memreq.addr + j]
# Create and enqueu response message
memresp = s.mem_ifc_dtypes.resp()
memresp.type_ = MemRespMsg.TYPE_READ
memresp.len = memreq.len
memresp.data = read_data
resp_q.enq(memresp)
# Handle a write request
elif memreq.type_ == MemReqMsg.TYPE_WRITE:
# Copy write data bits into bytearray
write_data = memreq.data
for j in range(nbytes):
s.mem[memreq.addr + j] = write_data[j * 8:j * 8 +
8].uint()
# Create and enqueu response message
memresp = s.mem_ifc_dtypes.resp()
memresp.type_ = MemRespMsg.TYPE_WRITE
memresp.len = 0
memresp.data = 0
resp_q.enq(memresp)
def __init__(s):
# Parameters
num_cores = 4
mopaque_nbits = 8
addr_nbits = 32
cacheline_nbits = 128
# Interface
s.memifc = MemMsg(mopaque_nbits, addr_nbits, cacheline_nbits)
s.mngr2proc = InValRdyBundle[num_cores](32)
s.proc2mngr = OutValRdyBundle[num_cores](32)
s.imemreq = OutValRdyBundle(s.memifc.req)
s.imemresp = InValRdyBundle(s.memifc.resp)
s.dmemreq = OutValRdyBundle(s.memifc.req)
s.dmemresp = InValRdyBundle(s.memifc.resp)
# These ports are for statistics. Basically we want to provide the
# simulator with some useful signals to let the simulator calculate
# cache miss rate.
s.stats_en = OutPort(1)
s.commit_inst = OutPort(num_cores)
s.icache_miss = OutPort(num_cores)
s.icache_access = OutPort(num_cores)
s.dcache_miss = OutPort(num_cores)
s.dcache_access = OutPort(num_cores)
# Connection
s.inner = MultiCoreVRTL_inner()
memreq_nbits = s.memifc.req.nbits
memresp_nbits = s.memifc.resp.nbits
for i in xrange(num_cores):
s.connect_pairs(
s.mngr2proc[i].val,
s.inner.mngr2proc_val[i],
s.mngr2proc[i].rdy,
s.inner.mngr2proc_rdy[i],
s.mngr2proc[i].msg,
s.inner.mngr2proc_msg[i * 32:(i + 1) * 32],
s.proc2mngr[i].val,
s.inner.proc2mngr_val[i],
s.proc2mngr[i].rdy,
s.inner.proc2mngr_rdy[i],
s.proc2mngr[i].msg,
s.inner.proc2mngr_msg[i * 32:(i + 1) * 32],
s.imemreq,
s.inner.imemreq,
s.imemresp,
s.inner.imemresp,
s.dmemreq,
s.inner.dmemreq,
s.dmemresp,
s.inner.dmemresp,
s.stats_en,
s.inner.stats_en,
s.commit_inst,
s.inner.commit_inst,
s.icache_miss,
s.inner.icache_miss,
s.icache_access,
s.inner.icache_access,
s.dcache_miss,
s.inner.dcache_miss,
s.dcache_access,
s.inner.dcache_access,
)
def __init__(s):
# Parameters
num_cores = 4
mopaque_nbits = 8
addr_nbits = 32
cacheline_nbits = 128
# Interface
s.memifc = MemMsg(mopaque_nbits, addr_nbits, cacheline_nbits)
s.mngr2proc_val = InPort(num_cores)
s.mngr2proc_rdy = OutPort(num_cores)
s.mngr2proc_msg = InPort(32 * num_cores)
s.proc2mngr_val = OutPort(num_cores)
s.proc2mngr_rdy = InPort(num_cores)
s.proc2mngr_msg = OutPort(32 * num_cores)
s.imemreq = OutValRdyBundle(s.memifc.req)
s.imemresp = InValRdyBundle(s.memifc.resp)
s.dmemreq = OutValRdyBundle(s.memifc.req)
s.dmemresp = InValRdyBundle(s.memifc.resp)
s.stats_en = OutPort(1)
s.commit_inst = OutPort(num_cores)
s.icache_miss = OutPort(num_cores)
s.icache_access = OutPort(num_cores)
s.dcache_miss = OutPort(num_cores)
s.dcache_access = OutPort(num_cores)
# connect to Verilog module
s.set_ports({
'clk': s.clk,
'reset': s.reset,
'mngr2proc_val': s.mngr2proc_val,
'mngr2proc_rdy': s.mngr2proc_rdy,
'mngr2proc_msg': s.mngr2proc_msg,
'proc2mngr_val': s.proc2mngr_val,
'proc2mngr_rdy': s.proc2mngr_rdy,
'proc2mngr_msg': s.proc2mngr_msg,
'imemreq_val': s.imemreq.val,
'imemreq_rdy': s.imemreq.rdy,
'imemreq_msg': s.imemreq.msg,
'imemresp_val': s.imemresp.val,
'imemresp_rdy': s.imemresp.rdy,
'imemresp_msg': s.imemresp.msg,
'dmemreq_val': s.dmemreq.val,
'dmemreq_rdy': s.dmemreq.rdy,
'dmemreq_msg': s.dmemreq.msg,
'dmemresp_val': s.dmemresp.val,
'dmemresp_rdy': s.dmemresp.rdy,
'dmemresp_msg': s.dmemresp.msg,
'stats_en': s.stats_en,
'commit_inst': s.commit_inst,
'icache_miss': s.icache_miss,
'icache_access': s.icache_access,
'dcache_miss': s.dcache_miss,
'dcache_access': s.dcache_access,
})
def __init__( s ):
# Parameters
num_cores = 1
opaque_nbits = 8
addr_nbits = 32
icache_nbytes = 256
dcache_nbytes = 256
data_nbits = 32
cacheline_nbits = 128
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.memifc = MemMsg( opaque_nbits, addr_nbits, cacheline_nbits )
s.mngr2proc = InValRdyBundle ( 32 )
s.proc2mngr = OutValRdyBundle( 32 )
s.imemreq = OutValRdyBundle( s.memifc.req )
s.imemresp = InValRdyBundle ( s.memifc.resp )
s.dmemreq = OutValRdyBundle( s.memifc.req )
s.dmemresp = InValRdyBundle ( s.memifc.resp )
# These ports are for statistics. Basically we want to provide the
# simulator with some useful signals to let the simulator calculate
# cache miss rate.
s.stats_en = OutPort( 1 )
s.commit_inst = OutPort( 1 )
s.icache_miss = OutPort( 1 )
s.icache_access = OutPort( 1 )
s.dcache_miss = OutPort( 1 )
s.dcache_access = OutPort( 1 )
#---------------------------------------------------------------------
# Components
#---------------------------------------------------------------------
s.proc = ProcAltRTL( num_cores )
s.icache = BlockingCacheAltRTL( 0 )
s.dcache = BlockingCacheAltRTL( 0 )
#---------------------------------------------------------------------
# Connections
#---------------------------------------------------------------------
# core id & mngr
s.connect( s.proc.core_id, 0 )
s.connect( s.mngr2proc, s.proc.mngr2proc )
s.connect( s.proc2mngr, s.proc.proc2mngr )
# instruction
s.connect( s.proc.imemreq, s.icache.cachereq )
s.connect( s.icache.memreq, s.imemreq )
s.connect( s.proc.imemresp, s.icache.cacheresp )
s.connect( s.icache.memresp, s.imemresp )
# data
s.connect( s.proc.dmemreq, s.dcache.cachereq )
s.connect( s.dcache.memreq, s.dmemreq )
s.connect( s.proc.dmemresp, s.dcache.cacheresp )
s.connect( s.dcache.memresp, s.dmemresp )
# statistics
s.connect( s.stats_en, s.proc.stats_en )
s.connect( s.commit_inst, s.proc.commit_inst )
@s.combinational
def collect_cache_statistics():
s.icache_miss.value = s.icache.cacheresp.rdy & s.icache.cacheresp.val & \
(~s.icache.cacheresp.msg.test[0])
s.icache_access.value = s.icache.cachereq.rdy & s.icache.cachereq.val
s.dcache_miss.value = s.dcache.cacheresp.rdy & s.dcache.cacheresp.val & \
(~s.dcache.cacheresp.msg.test[0])
s.dcache_access.value = s.dcache.cachereq.rdy & s.dcache.cachereq.val
def __init__(s):
# interface from source and sink
s.in_mem = InValRdyBundle(nWid)
s.out_mem = OutValRdyBundle(nWid)
s.cgra = CgraRTL()
s.fsm = fsm()
#Memory
s.ocm = TestMemoryFuture(MemMsg(
0, 32, nWid)) # opaque field, address, data width
# Input Mux
s.input_mux = m = Mux(dtype=MemMsg(0, 32, nWid), nports=3)
s.in_mem_wire = Wire(MemMsg(0, 32, nWid))
@s.combinational
def logic():
s.in_mem_wire.msg[0:16].value = s.in_mem.msg[0:16] # data
s.in_mem_wire.msg[16:18].value = s.in_mem.msg[
16:18] # length in bytes of read or write
s.in_mem_wire.msg[18:50].value = s.in_mem.msg[18:
50] # address field
s.in_mem_wire.msg[50:51].value = s.in_mem.msg[
50:51] # type: read or write
s.connect_pairs(
m.in_[0],
s.in_mem_wire,
m.in_[1],
s.cgra.ocmreqs[0],
m.in_[2],
s.cgra.ocmreqs[1],
m.sel,
s.fsm.in_mux_sel, # Add later in Cpath
)
# Memory Connections
s.connect(s.ocm.reqs[0], s.input_mux.out)
# Demux logic
@s.combinational
def logic():
if s.fsm.out_mux_sel.value == 0:
s.out_mem.msg[0:16] = s.ocm.resps[0].msg[0:16]
s.out_mem.msg[16:18] = s.ocm.resps[0].msg[16:18]
s.out_mem.msg[18:50] = s.ocm.resps[0].msg[18:50]
s.out_mem.msg[50:51] = s.ocm.resps[0].msg[50:51]
elif s.fsm.out_mux_sel.value == 1:
s.cgra.ocmresps[0].msg.value = s.ocm.resps[0].msg
elif s.fsm.out_mux_sel.value == 2:
s.cgra.ocmresps[1].msg.value = s.ocm.resps[0].msg
# queue for control word
#s.ctr_q = SingleElementBypassQueue[nPE](inst_msg())
#s.ctr_q = SingleElementNormalQueue[nPE](inst_msg())
s.ctr_q = NormalQueue[nPE](2, inst_msg())
# queue for cgra-to-fsm response
s.resp_q = SingleElementBypassQueue[nPE](1)
#s.resp_q = SingleElementNormalQueue[nPE](1)
for x in range(nPE):
s.connect(s.cgra.out_fsm[x], s.resp_q[x].enq)
s.connect(s.resp_q[x].deq, s.fsm.in_[x])
s.connect(s.fsm.out[x], s.ctr_q[x].enq)
s.connect(s.ctr_q[x].deq, s.cgra.in_control[x])
s.connect(s.in_mem, s.cgra.in_mem)
s.connect(s.out_mem, s.cgra.out_mem)
def __init__(s):
# Parameters
num_reqers = 4 # 4 processors
num_reqees = 4 # 4 data caches
num_ports = max(num_reqers, num_reqees) # We still have 4 ports
nopaque_nbits = 8
mopaque_nbits = 8
addr_nbits = 32
data_nbits = 32 # CacheNet only deals with 32 bit requests
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.procifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.cacheifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.procreq = InValRdyBundle[num_ports](s.procifc.req)
s.procresp = OutValRdyBundle[num_ports](s.procifc.resp)
s.cachereq = OutValRdyBundle[num_ports](s.cacheifc.req)
s.cacheresp = InValRdyBundle[num_ports](s.cacheifc.resp)
#---------------------------------------------------------------------
# Components
#---------------------------------------------------------------------
single_reqee = False # 4 caches so not single reqee
single_reqer = False # 4 procs so not single reqer
s.u_adpt = UpsAdapter[num_ports](
single_reqee,
mopaque_nbits,
addr_nbits,
data_nbits, # mem msg parameter
nopaque_nbits,
num_ports) # net msg parameter
# One can also use RingNetRTL
s.reqnet = BusNetRTL(s.procifc.req.nbits)
s.respnet = BusNetRTL(s.procifc.resp.nbits)
s.d_adpt = DownsAdapter[num_ports](
single_reqer,
mopaque_nbits,
addr_nbits,
data_nbits, # mem msg parameter
nopaque_nbits,
num_ports) # net msg parameter
#---------------------------------------------------------------------
# Connections
#---------------------------------------------------------------------
for i in xrange(num_ports):
s.connect(s.u_adpt[i].src_id, i)
s.connect(s.procreq[i], s.u_adpt[i].memreq)
s.connect(s.u_adpt[i].netreq, s.reqnet.in_[i])
s.connect(s.procresp[i], s.u_adpt[i].memresp)
s.connect(s.u_adpt[i].netresp, s.respnet.out[i])
for i in xrange(num_ports):
s.connect(s.d_adpt[i].src_id, i)
s.connect(s.reqnet.out[i], s.d_adpt[i].netreq)
s.connect(s.d_adpt[i].memreq, s.cachereq[i])
s.connect(s.respnet.in_[i], s.d_adpt[i].netresp)
s.connect(s.d_adpt[i].memresp, s.cacheresp[i])
def __init__(s):
# Parameters
num_reqers = 4 # 4 data caches
num_reqees = 1 # 1 memory port
num_ports = max(num_reqers, num_reqees) # We still have 4 ports
nopaque_nbits = 8
mopaque_nbits = 8
addr_nbits = 32
data_nbits = 128 # MemNet deals with 128 bit refill requests
# Interface
s.memifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.mainmemifc = MemMsg(mopaque_nbits, addr_nbits, data_nbits)
s.memreq = InValRdyBundle[num_ports](s.memifc.req)
s.memresp = OutValRdyBundle[num_ports](s.memifc.resp)
s.mainmemreq = OutValRdyBundle[num_ports](s.mainmemifc.req)
s.mainmemresp = InValRdyBundle[num_ports](s.mainmemifc.resp)
# Connection
s.inner = MemNetVRTL_inner()
memreq_nbits = s.memifc.req.nbits
memresp_nbits = s.memifc.resp.nbits
mainmemreq_nbits = s.mainmemifc.req.nbits
mainmemresp_nbits = s.mainmemifc.resp.nbits
for i in xrange(num_ports):
s.connect_pairs(
s.memreq[i].val,
s.inner.memreq_val[i],
s.memreq[i].rdy,
s.inner.memreq_rdy[i],
s.memreq[i].msg,
s.inner.memreq_msg[i * memreq_nbits:(i + 1) * memreq_nbits],
s.memresp[i].val,
s.inner.memresp_val[i],
s.memresp[i].rdy,
s.inner.memresp_rdy[i],
s.memresp[i].msg,
s.inner.memresp_msg[i * memresp_nbits:(i + 1) * memresp_nbits],
s.mainmemreq[i].val,
s.inner.mainmemreq_val[i],
s.mainmemreq[i].rdy,
s.inner.mainmemreq_rdy[i],
s.mainmemreq[i].msg,
s.inner.mainmemreq_msg[i * mainmemreq_nbits:(i + 1) *
mainmemreq_nbits],
s.mainmemresp[i].val,
s.inner.mainmemresp_val[i],
s.mainmemresp[i].rdy,
s.inner.mainmemresp_rdy[i],
s.mainmemresp[i].msg,
s.inner.mainmemresp_msg[i * mainmemresp_nbits:(i + 1) *
mainmemresp_nbits],
)
