def __init__(self, peak_generator):
pe = peak_generator(hwtypes.BitVector.get_family())
assert issubclass(pe, peak.Peak)
pe = pe.__call__
(self.__instr_name, self.__instr_type) = pe._peak_isa_
self.__inputs = pe._peak_inputs_
self.__outputs = pe._peak_outputs_
circuit = peak_generator(magma.get_family())
self.__asm, disasm, self.__instr_width, layout = \
peak.auto_assembler.generate_assembler(self.__instr_type)
instr_magma_type = type(circuit.interface.ports[self.__instr_name])
self.__circuit = peak.wrap_with_disassembler(circuit, disasm,
self.__instr_width,
HashableDict(layout),
instr_magma_type)
def __init__(self, peak_generator):
pe = peak_generator(PyFamily())
assert issubclass(pe, peak.Peak)
self._model = pe()
#Lassen's name for the ISA is 'inst', so this is hardcoded
self.__instr_name = 'inst'
self.__instr_type = strip_modifiers(pe.input_t.field_dict['inst'])
self.__inputs = OrderedDict(pe.input_t.field_dict)
del self.__inputs['inst']
self.__outputs = OrderedDict(pe.output_t.field_dict)
circuit = peak_generator(MagmaFamily())
self.__asm = Assembler(self.__instr_type)
instr_magma_type = type(circuit.interface.ports[self.__instr_name])
self.__circuit = peak.wrap_with_disassembler(
circuit, self.__asm.disassemble, self.__asm.width,
HashableDict(self.__asm.layout), instr_magma_type)
data_gate(self.__circuit)
def test_wrapped_PE():
class HashableDict(dict):
def __hash__(self):
return hash(tuple(sorted(self.keys())))
pe = PE_fc(PyFamily())
#Lassen's name for the ISA is 'inst', so this is hardcoded
__instr_name = 'inst'
__instr_type = pe.input_t.field_dict['inst']
__inputs = OrderedDict(pe.input_t.field_dict)
__inputs['inst']
__outputs = OrderedDict(pe.output_t.field_dict)
circuit = PE_fc(MagmaFamily())
__asm = Assembler(__instr_type)
instr_magma_type = type(circuit.interface.ports[__instr_name])
__circuit = peak.wrap_with_disassembler(circuit, __asm.disassemble,
__asm.width,
HashableDict(__asm.layout),
instr_magma_type)
assert __circuit is not None
Data = BitVector[DATAWIDTH]
# create these variables in global space so that we can reuse them easily
inst_name = 'inst'
inst_type = PE_bv.input_t.field_dict[inst_name]
_assembler = Assembler(inst_type)
assembler = _assembler.assemble
disassembler = _assembler.disassemble
width = _assembler.width
layout = _assembler.layout
#PE_magma = PE_fc(MagmaFamily(), use_assembler=True)
PE_magma = PE_fc(MagmaFamily())
instr_magma_type = type(PE_magma.interface.ports[inst_name])
pe_circuit = wrap_with_disassembler(PE_magma, disassembler, width,
HashableDict(layout),
instr_magma_type)
tester = fault.Tester(pe_circuit, clock=pe_circuit.CLK)
test_dir = "tests/build"
# Explicitly load `float_DW` lib so we get technology specific mapping with
# special code for BFloat rounding, for more info:
# * https://github.com/rdaly525/coreir/pull/753
# * https://github.com/StanfordAHA/lassen/issues/111
# We reset the context because tests/test_micro.py calls compile and pollutes
# the coreir context causing a "redefinition of module" error
magma.backend.coreir_.CoreIRContextSingleton().reset_instance()
magma.compile(f"{test_dir}/WrappedPE", pe_circuit, output="coreir-verilog",
coreir_libs={"float_DW"})
# check if we need to use ncsim + cw IP