示例#1
0
 def __process_array(self, context, array, segments, pos_in_top):
     hierarchy = analyze_hierarchy(context)
     for pos, instance in iteritems(array.element_instances):
         module = instance.model
         if module.module_class.is_tile:
             if module.name in self.visited:
                 continue
             self.visited.add(module.name)
             cboxify(context.connection_box_library, module, segments,
                     self.block_fc.get(module.block.name, self.default_fc), module.orientation.opposite)
             for (cbox_pos, orientation), cbox in iteritems(module.cbox_instances):
                 if cbox.model.name in hierarchy[module.name]:
                     continue
                 generate_fc(cbox.model, segments, module.block, orientation,
                         self.block_fc.get(module.block.name, self.default_fc),
                         cbox_pos, orientation.case((0, 0), (0, 0), (0, -1), (-1, 0)))
                 hierarchy.setdefault(cbox.model.name, {})
                 hierarchy[module.name][cbox.model.name] = cbox.model
         elif module.module_class.is_array:
             self.__process_array(context, module, segments, pos + pos_in_top)
     sboxify(context.switch_box_library, array, context.top, pos_in_top)
     for sbox in itervalues(array.sbox_instances):
         if sbox.model.name in hierarchy[array.name]:
             continue
         generate_wilton(sbox.model, segments, cycle_free = self.cycle_free)
         hierarchy.setdefault(sbox.model.name, {})
         hierarchy[array.name][sbox.model.name] = sbox.model
示例#2
0
 def run(self, context):
     vgen = VerilogGenerator(context._additional_template_search_paths)
     hierarchy = analyze_hierarchy(context)
     visited = set()
     queue = {context.top.name: context.top}
     context._verilog_sources = []
     while queue:
         name, module = queue.popitem()
         visited.add(name)
         f = module.verilog_source
         if f is None:
             f = module.verilog_source = os.path.abspath(
                 os.path.join(self.prefix, name + '.v'))
         else:
             f = module.verilog_source = os.path.abspath(
                 os.path.join(self.prefix, module.verilog_source))
         _logger.info(
             "[RTLGEN] Generating Verilog for module '{}': {}".format(
                 name, f))
         makedirs(os.path.dirname(f))
         vgen.generate_module(open(f, OpenMode.wb), module)
         context._verilog_sources.append(f)
         for subname, sub in iteritems(hierarchy[name]):
             if subname in visited or subname in queue or not sub.in_physical_domain:
                 continue
             queue[subname] = sub
示例#3
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 def run(self, context):
     hierarchy = analyze_hierarchy(context)
     stack = {context.top.name: context.top}
     visited = set()
     while stack:
         name, module = stack.popitem()
         visited.add(name)
         if module.module_class in (ModuleClass.cluster,
                                    ModuleClass.io_block,
                                    ModuleClass.logic_block):
             for instance in itervalues(module.instances):
                 if instance.module_class.is_primitive and instance.model.primitive_class.is_lut:
                     for bit in instance.pins['in']:
                         sources = tuple(iter(bit.user_sources))
                         bit.remove_user_sources()
                         bit.add_user_sources((ZERO, ) + sources)
         for subname, submod in iteritems(hierarchy[name]):
             if subname in stack or subname in visited:
                 continue
             elif submod.module_class not in (ModuleClass.array,
                                              ModuleClass.tile,
                                              ModuleClass.io_block,
                                              ModuleClass.logic_block,
                                              ModuleClass.cluster):
                 continue
             stack[subname] = submod
示例#4
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 def __process_array(self, context, array, top = False):
     hierarchy = analyze_hierarchy(context)
     for module in itervalues(hierarchy[array.name]):
         if module.name in self._visited:
             continue
         self._visited.add(module.name)
         if module.module_class.is_tile:
             netify_tile(module, self._directs)
         elif module.module_class.is_array:
             self.__process_array(context, module)
     netify_array(array, top)
示例#5
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 def run(self, context):
     hierarchy = analyze_hierarchy(context)
     modules = list(chain(itervalues(context.clusters),
         itervalues(context.io_blocks),
         itervalues(context.logic_blocks),
         itervalues(context.connection_boxes),
         itervalues(context.switch_boxes)))
     for module in modules:
         switchify(context.switch_library, module)
         for inst in itervalues(module.all_instances):
             if inst.module_class.is_switch:
                 hierarchy.setdefault(inst.model.name, {})
                 hierarchy[module.name][inst.model.name] = inst.model
示例#6
0
 def run(self, context):
     hierarchy = analyze_hierarchy(context)
     stack = {context.top.name: context.top}
     visited = set()
     while stack:
         name, module = stack.popitem()
         visited.add(name)
         if module.module_class.is_connection_box:
             for port in itervalues(module.all_nodes):
                 if not (port.direction.is_output
                         and port.node.node_type.is_blockport_bridge):
                     continue
                 for bit in port:
                     sources = tuple(iter(bit.user_sources))
                     bit.remove_user_sources()
                     bit.add_user_sources((ZERO, ) + sources)