def camake(self):
try:
if(self.variables[0]['gogen']==0):
self.generatevirtualgraph()
fname1=self.textbox1.text()
pins=self.variables[0]['pins']
ands_end=self.variables[0]['ands_end']
or_end=self.variables[0]['or_end']
nots_end=self.variables[0]['nots_end']
ops=self.variables[0]['ops']
wires1=self.variables[0]['wires1']
connection_and=self.variables[0]['ca']
connection_or=self.variables[0]['co']
connection_not=self.variables[0]['cn']
top1=print_into_file(fname1,ops,pins,nots_end,ands_end,or_end,connection_and,connection_or,connection_not,1)
top2=print_into_file(fname1,ops,pins,nots_end,ands_end,or_end,connection_and,connection_or,connection_not,2)
top3=print_into_file(fname1,ops,pins,nots_end,ands_end,or_end,connection_and,connection_or,connection_not,3)
#p1 = Process(target=find_and_gates_parallel, args=())
#p1.start()
#top1=ansav['rt']
#p2 = Process(target=find_and_gates_parallel, args=())
#p2.start()
#top1=ansav['rt']
#p3 = Process(target=find_and_gates_parallel, args=())
#p3.start()
#top1=ansav['rt']
str1=''
str1=str1+'######################################\n'
str1=str1+'########### Running parallelly ########\n'
str1=str1+'######################################\n'
ts='Finding the correct order in which the wires should be assigned for verilog files\n'
for vi in range(200):
ts=ts+'#'
self.variables[0]['text']=ts
self.textbox.setText(self.variables[0]['text'])
QApplication.processEvents()
timesleep=0.002
divide=1.0
if(self.ppchb.isChecked()):
divide=float(self.ppinp.text())
sleep(timesleep/divide)
str1=str1+ '\n\n'+top1+ '\n\n'
str1=str1+ '\n\n'+top2+ '\n\n'
str1=str1+ '\n\n'+top3+ '\n\n'
str1=str1+'######################################\n'
str1=str1+'########### Running Parallely ########\n'
str1=str1+'######################################\n\n\n\n'
str1=str1+'######################################\n'
str1=str1+'########### File saved as '+ self.textbox1.text()+'.verilog and in 2 other formats ########\n'
str1=str1+'######################################\n\n\n'
self.variables[0]['text']=str1
self.textbox.setText(self.variables[0]['text'])
except:
self.variables[0]['text']='Please Select A CIRC FILE'
self.textbox.setText(self.variables[0]['text'])
def abased(self):
try:
if(self.variables[0]['gogen']==0):
self.generatevirtualgraph()
fname1=self.textbox1.text()
pins=self.variables[0]['pins']
ands_end=self.variables[0]['ands_end']
or_end=self.variables[0]['or_end']
nots_end=self.variables[0]['nots_end']
ops=self.variables[0]['ops']
wires1=self.variables[0]['wires1']
connection_and=self.variables[0]['ca']
connection_or=self.variables[0]['co']
connection_not=self.variables[0]['cn']
top=print_into_file(fname1,ops,pins,nots_end,ands_end,or_end,connection_and,connection_or,connection_not,3)
str1=''
str1=str1+'######################################\n'
str1=str1+'########### Assign based Verilog ########\n'
str1=str1+'######################################\n'
ts='Finding the correct order in which the wires should be assigned for verilog files\n'
for vi in range(200):
ts=ts+'#'
self.variables[0]['text']=ts
self.textbox.setText(self.variables[0]['text'])
QApplication.processEvents()
timesleep=0.005
divide=1.0
if(self.ppchb.isChecked()):
divide=float(self.ppinp.text())
sleep(timesleep/divide)
str1=str1+top
str1=str1+'######################################\n'
str1=str1+'########### Assign based Verilog ########\n'
str1=str1+'######################################\n\n\n\n'
str1=str1+'######################################\n'
str1=str1+'########### File saved as '+ self.textbox1.text()+'.verilog and in 2 other formats ########\n'
str1=str1+'######################################\n\n\n'
self.variables[0]['text']=str1
self.textbox.setText(self.variables[0]['text'])
except:
self.variables[0]['text']='Please Select A CIRC FILE'
self.textbox.setText(self.variables[0]['text'])
def ttbased(self):
try:
if(self.variables[0]['gogen']==0):
self.generatevirtualgraph()
fname1=self.textbox1.text()
pins=self.variables[0]['pins']
ands_end=self.variables[0]['ands_end']
or_end=self.variables[0]['or_end']
nots_end=self.variables[0]['nots_end']
ops=self.variables[0]['ops']
wires1=self.variables[0]['wires1']
connection_and=self.variables[0]['ca']
connection_or=self.variables[0]['co']
connection_not=self.variables[0]['cn']
top=print_into_file(fname1,ops,pins,nots_end,ands_end,or_end,connection_and,connection_or,connection_not,2)
str1=''
str1=str1+'######################################\n'
str1=str1+'########### Truth Table based Verilog ########\n'
str1=str1+'######################################\n'
ts='Calculating all the possible combination for the truth table of the verilog file\n'
for vi in range(200):
ts=ts+'#'
self.variables[0]['text']=ts
self.textbox.setText(self.variables[0]['text'])
QApplication.processEvents()
sleep(0.005)
str1=str1+top
str1=str1+'######################################\n'
str1=str1+'########### Truth Table based Verilog ########\n'
str1=str1+'######################################\n\n\n\n'
str1=str1+'######################################\n'
str1=str1+'########### File saved as '+ self.textbox1.text()+'.verilog and in 2 other formats ########\n'
str1=str1+'######################################\n\n\n'
self.variables[0]['text']=str1
self.textbox.setText(self.variables[0]['text'])
except:
self.variables[0]['text']='Please Select A CIRC FILE'
self.textbox.setText(self.variables[0]['text'])
x2=connection_or[temp+'left']
connection_or.pop(temp+'right', None)
connection_or.pop(temp+'left', None)
connection_or[i+'right']=x1
connection_or[i+'left']=x2
for i in ops:
temp=ops_end[i]
if(temp in connection_not):
x1=connection_not[temp]
connection_not.pop(temp, None)
connection_not[i]=x1
#print 'connections'
#print 'connections not'
#print connection_not
#print 'connections and'
#for i in connection_and:
# print (i,connection_and[i])
#print 'connections or'
#for i in connection_or:
# print (i,connection_or[i])
print_into_file('output/first_file',ops,pins,nots_end,ands_end,or_end,connection_and,connection_or,connection_not)