def create_pulse_lib(awgs):
pulse = pulselib(backend='M3202A')
channels = []
# add to pulse_lib
for i, awg in enumerate(awgs):
pulse.add_awgs(awg.name, awg)
# define channels
for ch in range(1, 5):
channel_name = f'{awg.name}_{ch}'
pulse.define_channel(channel_name, awg.name, ch)
channels.append(channel_name)
n_ch = len(channels)
# set a virtual gate matrix
virtual_gate_set_1 = virtual_gates_constructor(pulse)
virtual_gate_set_1.add_real_gates(*channels)
virtual_gate_set_1.add_virtual_gates(*[f'vP{i+1}' for i in range(n_ch)])
# copy data of AWG1 to all other AWG
inv_matrix = np.zeros((n_ch, ) * 2)
for i in range(4):
inv_matrix[i::4, i] = 1.0
for i in range(4, n_ch):
inv_matrix[i, i] = 1.0
virtual_gate_set_1.add_virtual_gate_matrix(np.linalg.inv(inv_matrix))
pulse.finish_init()
return pulse
def init_pulselib(awgs, virtual_gates=False, bias_T_rc_time=None):
pulse = pulselib()
for awg in awgs:
pulse.add_awgs(awg.name, awg)
# define channels
pulse.define_channel('P1', 'AWG1', 1)
pulse.define_channel('P2', 'AWG1', 2)
# add limits on voltages for DC channel compenstation (if no limit is specified, no compensation is performed).
pulse.add_channel_compensation_limit('P1', (-200, 500))
pulse.add_channel_compensation_limit('P2', (-200, 500))
if bias_T_rc_time:
pulse.add_channel_bias_T_compensation('P1', bias_T_rc_time)
pulse.add_channel_bias_T_compensation('P2', bias_T_rc_time)
if virtual_gates:
# set a virtual gate matrix
virtual_gate_set_1 = virtual_gates_constructor(pulse)
virtual_gate_set_1.add_real_gates('P1', 'P2')
virtual_gate_set_1.add_virtual_gates('vP1', 'vP2')
inv_matrix = 1.2 * np.eye(2) - 0.1
virtual_gate_set_1.add_virtual_gate_matrix(np.linalg.inv(inv_matrix))
pulse.finish_init()
return pulse
def init_pulselib(awgs, digitizer):
p = pulselib(backend='Keysight_QS')
for awg in awgs:
p.add_awg(awg)
p.add_digitizer(digitizer)
awg1, awg2 = awgs
p.define_channel('P1', awg1.name, 1)
p.define_channel('P2', awg1.name, 2)
p.define_channel('P3', awg1.name, 3)
p.define_channel('P4', awg1.name, 4)
set_channel_props(p, 'P1', compensation_limits=(-500,500), attenuation=2.0, delay=0, bias_T_rc_time=0.001)
set_channel_props(p, 'P2', compensation_limits=(-250,250), attenuation=1.0, delay=0, bias_T_rc_time=0.001)
set_channel_props(p, 'P3', compensation_limits=(-280,280), attenuation=1.0, delay=0, bias_T_rc_time=0.001)
set_channel_props(p, 'P4', bias_T_rc_time=0.001)
p.define_digitizer_channel('SE1', digitizer.name, 1)
p.finish_init()
# add virtual channels.
virtual_gate_set_1 = virtual_gates_constructor(p)
virtual_gate_set_1.add_real_gates('P1','P2','P3','P4')
virtual_gate_set_1.add_virtual_gates('vP1','vP2','vP3','vP4')
virtual_gate_set_1.add_virtual_gate_matrix(0.9*np.eye(4) + 0.1)
return p
def load_hardware(self, hardware):
'''
load virtual gates and attenuation via the harware class (used in qtt)
Args:
hardware (harware_parent) : harware class.
'''
for virtual_gate_set in hardware.virtual_gates:
vgc = virtual_gates_constructor(self)
vgc.load_via_harware(virtual_gate_set)
# set output ratio's of the channels from the harware file.
if self.AWG_to_dac_ratio.keys() == hardware.AWG_to_dac_conversion.keys():
self.AWG_to_dac_ratio = hardware.AWG_to_dac_conversion
else:
hardware.AWG_to_dac_conversion = self.AWG_to_dac_ratio
hardware.sync_data()
def init_pulselib(awgs, virtual_gates=False, bias_T_rc_time=None):
pulse = pulselib()
for awg in awgs:
pulse.add_awg(awg)
# define channels
pulse.define_channel('P1','AWG1', 1)
pulse.define_channel('P2','AWG1', 2)
pulse.define_channel('I1','AWG1', 3)
pulse.define_channel('Q1','AWG1', 4)
pulse.define_digitizer_channel('SD1', 'Digitizer', 1)
# add limits on voltages for DC channel compensation (if no limit is specified, no compensation is performed).
pulse.add_channel_compensation_limit('P1', (-200, 500))
pulse.add_channel_compensation_limit('P2', (-200, 500))
if bias_T_rc_time:
pulse.add_channel_bias_T_compensation('P1', bias_T_rc_time)
pulse.add_channel_bias_T_compensation('P2', bias_T_rc_time)
if virtual_gates:
# set a virtual gate matrix
virtual_gate_set_1 = virtual_gates_constructor(pulse)
virtual_gate_set_1.add_real_gates('P1','P2')
virtual_gate_set_1.add_virtual_gates('vP1','vP2')
inv_matrix = 1.2*np.eye(2) - 0.1
virtual_gate_set_1.add_virtual_gate_matrix(np.linalg.inv(inv_matrix))
# define IQ output pair
IQ_pair_1 = IQ_channel_constructor(pulse)
IQ_pair_1.add_IQ_chan("I1", "I")
IQ_pair_1.add_IQ_chan("Q1", "Q")
# frequency of the MW source
IQ_pair_1.set_LO(2.40e9)
# add 1 qubit: q1
IQ_pair_1.add_virtual_IQ_channel("q1")
pulse.finish_init()
return pulse
def return_pulse_lib():
pulse = pulselib()
# add to pulse_lib
# pulse.add_awgs('AWG1',None)
# pulse.add_awgs('AWG2',None)
# pulse.add_awgs('AWG3',None)
# pulse.add_awgs('AWG4',None)
# define channels
pulse.define_channel('B3', 'AWG1', 1)
pulse.define_channel('B4', 'AWG1', 2)
pulse.define_channel('P5', 'AWG1', 3)
pulse.define_channel('P4', 'AWG1', 4)
pulse.define_channel('P1', 'AWG2', 1)
pulse.define_channel('B1', 'AWG2', 2)
pulse.define_channel('P2', 'AWG2', 3)
pulse.define_channel('B0', 'AWG2', 4)
pulse.define_channel('B5', 'AWG3', 1)
pulse.define_channel('A2', 'AWG3', 2)
pulse.define_channel('A3', 'AWG3', 3)
pulse.define_channel('A4', 'AWG3', 4)
pulse.define_channel('A5', 'AWG4', 1)
pulse.define_channel('M1', 'AWG4', 2)
pulse.define_channel('A6', 'AWG4', 3)
pulse.define_marker('M2', 'AWG4', 4)
# format : channel name with delay in ns (can be posive/negative)
# pulse.add_channel_delay('I_MW',50)
# pulse.add_channel_delay('Q_MW',50)
# pulse.add_channel_delay('M1',20)
# pulse.add_channel_delay('M2',-25)
# add limits on voltages for DC channel compenstation (if no limit is specified, no compensation is performed).
pulse.add_channel_compensation_limit('B0', (-1000, 500))
pulse.add_channel_compensation_limit('B1', (-1000, 500))
pulse.add_channel_compensation_limit('B3', (-1000, 500))
pulse.add_channel_compensation_limit('B4', (-1000, 500))
pulse.add_channel_compensation_limit('P1', (-1000, 500))
pulse.add_channel_compensation_limit('P2', (-1000, 500))
pulse.add_channel_compensation_limit('P4', (-1000, 500))
pulse.add_channel_compensation_limit('P5', (-1000, 500))
pulse.add_channel_compensation_limit('B5', (-1000, 500))
# set a virtual gate matrix (note that you are not limited to one matrix if you would which so)
virtual_gate_set_1 = virtual_gates_constructor(pulse)
virtual_gate_set_1.add_real_gates('P4', 'P5', 'B3', 'B4', 'B5')
virtual_gate_set_1.add_virtual_gates('vP4', 'vP5', 'vB3', 'vB4', 'vB5')
virtual_gate_set_1.add_virtual_gate_matrix(np.eye(5))
# # make virtual channels for IQ usage (also here, make one one of these object per MW source)
# IQ_chan_set_1 = IQ_channel_constructor(pulse)
# # set right association of the real channels with I/Q output.
# IQ_chan_set_1.add_IQ_chan("I_MW", "I")
# IQ_chan_set_1.add_IQ_chan("Q_MW", "Q")
# IQ_chan_set_1.add_marker("M1", -15, 15)
# IQ_chan_set_1.add_marker("M2", -15, 15)
# # set LO frequency of the MW source. This can be changed troughout the experiments, bit only newly created segments will hold the latest value.
# IQ_chan_set_1.set_LO(1e9)
# # name virtual channels to be used.
# IQ_chan_set_1.add_virtual_IQ_channel("MW_qubit_1")
# IQ_chan_set_1.add_virtual_IQ_channel("MW_qubit_2")
# finish initialisation (! important if using keysight uploader)
# pulse.finish_init()
return pulse
# format : channel name with delay in ns (can be posive/negative)
p.add_channel_delay('I_MW', 50)
p.add_channel_delay('Q_MW', 50)
# add limits on voltages for DC channel compenstation (if no limit is specified, no compensation is performed).
# p.add_channel_compensation_limit('B0', (-100, 500))
try:
from V2_software.drivers.virtual_gates.harware import hardware_example
hw = hardware_example("hw")
p.load_hardware(hw)
except:
# set a virtual gate matrix (note that you are not limited to one matrix if you would which so)
virtual_gate_set_1 = virtual_gates_constructor(p)
virtual_gate_set_1.add_real_gates('P1', 'P2', 'P3', 'P4', 'P5', 'B0',
'B1', 'B2', 'B3', 'B4', 'B5')
virtual_gate_set_1.add_virtual_gates('vP1', 'vP2', 'vP3', 'vP4', 'vP5',
'vB0', 'vB1', 'vB2', 'vB3', 'vB4',
'vB5')
virtual_gate_set_1.add_virtual_gate_matrix(np.eye(11))
#make virtual channels for IQ usage (also here, make one one of these object per MW source)
IQ_chan_set_1 = IQ_channel_constructor(p)
# set right association of the real channels with I/Q output.
IQ_chan_set_1.add_IQ_chan("I_MW", "I")
IQ_chan_set_1.add_IQ_chan("Q_MW", "Q")
IQ_chan_set_1.add_marker("M1")
IQ_chan_set_1.add_marker("M2")
# set LO frequency of the MW source. This can be changed troughout the experiments, bit only newly created segments will hold the latest value.
def init_pulselib(awg1, awg2, awg3):
p = pulselib()
p.add_awg(awg1)
p.add_awg(awg2)
p.add_awg(awg3)
p.define_channel('P1', awg1.name, 1)
p.define_channel('P2', awg1.name, 2)
p.define_channel('P3', awg1.name, 3)
p.define_channel('P4', awg1.name, 4)
p.define_marker('M1', awg3.name, 3, setup_ns=40, hold_ns=20)
p.define_marker('M2', awg3.name, 0, setup_ns=40, hold_ns=20)
set_channel_props(p,
'P1',
compensation_limits=(-100, 100),
attenuation=2.0,
delay=0)
set_channel_props(p,
'P2',
compensation_limits=(-50, 50),
attenuation=1.0,
delay=0)
set_channel_props(p,
'P3',
compensation_limits=(-80, 80),
attenuation=1.0,
delay=0)
p.define_channel('I1', awg2.name, 1)
p.define_channel('Q1', awg2.name, 2)
p.define_channel('I2', awg2.name, 3)
p.define_channel('Q2', awg2.name, 4)
set_channel_props(p,
'I1',
compensation_limits=(-80, 80),
attenuation=1.0,
delay=0)
p.finish_init()
# add virtual channels.
virtual_gate_set_1 = virtual_gates_constructor(p)
virtual_gate_set_1.add_real_gates('P1', 'P2', 'P3', 'P4')
virtual_gate_set_1.add_virtual_gates('vP1', 'vP2', 'vP3', 'vP4')
virtual_gate_set_1.add_virtual_gate_matrix(0.9 * np.eye(4) + 0.1)
#make virtual channels for IQ usage (also here, make one one of these object per MW source)
IQ_chan_set_1 = IQ_channel_constructor(p)
# set right association of the real channels with I/Q output.
IQ_chan_set_1.add_IQ_chan("I1", "I")
IQ_chan_set_1.add_IQ_chan("Q1", "Q")
IQ_chan_set_1.add_marker("M1")
# frequency of the MW source
IQ_chan_set_1.set_LO(2e9)
IQ_chan_set_1.add_virtual_IQ_channel("MW_qubit_1")
IQ_chan_set_1.add_virtual_IQ_channel("MW_qubit_2")
IQ_chan_set_2 = IQ_channel_constructor(p)
# set right association of the real channels with I/Q output.
IQ_chan_set_2.add_IQ_chan("I2", "I")
IQ_chan_set_2.add_IQ_chan("Q2", "Q")
IQ_chan_set_2.add_marker("M2")
# frequency of the MW source
IQ_chan_set_2.set_LO(2e9)
IQ_chan_set_2.add_virtual_IQ_channel("MW_qubit_3")
IQ_chan_set_2.add_virtual_IQ_channel("MW_qubit_4")
return p
