def test_circuit_basis(): m1 = DefModule("m1", [OutputPort("p", uw(8))], Connect(n("p", uw(8)), u(2, w(8)))) m2 = DefModule( "m2", [InputPort("b", uw(8)), OutputPort("a", uw(8))], Block([ DefNode("n", u(1, w(1))), Conditionally(n("n", uw(1)), EmptyStmt(), Connect(n("a", uw(8)), n("b", uw(8)))) ])) ct = DefCircuit("m1", [m1, m2]) assert check(ct) serialize_stmt_equal( ct, 'circuit m1 :\n' ' module m1 :\n' ' output p : UInt<8>\n' '\n' ' p <= UInt<8>("h2")\n' '\n' ' module m2 :\n' ' input b : UInt<8>\n' ' output a : UInt<8>\n' '\n' ' node n = UInt<1>("h1")\n' ' when n :\n' ' skip\n' ' else :\n' ' a <= b\n' '\n')
def test_module_basis(): mod = DefModule("m", [OutputPort("p", uw(8))], Connect(n("p", uw(8)), u(2, w(8)))) assert check(mod) serialize_stmt_equal( mod, 'module m :\n' ' output p : UInt<8>\n' '\n' ' p <= UInt<8>("h2")') mod = DefModule( "m", [InputPort("b", uw(8)), OutputPort("a", uw(8))], Block([ DefNode("n", u(1, w(1))), Conditionally(n("n", uw(1)), EmptyStmt(), Connect(n("a", uw(8)), n("b", uw(8)))) ])) assert check(mod) serialize_stmt_equal( mod, 'module m :\n' ' input b : UInt<8>\n' ' output a : UInt<8>\n' '\n' ' node n = UInt<1>("h1")\n' ' when n :\n' ' skip\n' ' else :\n' ' a <= b')
def test_connect_type_wrong(): cn = Connect(n("a", uw(8)), n("b", sw(8))) assert not check(cn) cn = Connect(n("a", sw(8)), n("b", uw(8))) assert not check(cn) cn = Connect(n("a", uw(8)), s(20, w(8))) assert not check(cn) cn = Connect(n("a", sw(8)), n(-20, w(8))) assert not check(cn)
def test_conditionally_type_wrong(): s1 = EmptyStmt() s2 = Connect(n("a", uw(8)), n("b", uw(8))) cn = Conditionally(n("a", sw(1)), s1, s2) assert not check(cn) s1 = Block([ Connect(n("a", uw(8)), n("b", uw(8))), Connect(n("c", sw(8)), n("d", sw(8))), ]) s2 = EmptyStmt() cn = Conditionally(u(1, w(2)), s1, s2) assert not check(cn)
def test_circuit_module_not_exist(): m1 = DefModule("m1", [OutputPort("p", uw(8))], Connect(n("p", uw(8)), u(2, w(8)))) m2 = DefModule( "m2", [InputPort("b", uw(8)), OutputPort("a", uw(8))], Block([ DefNode("n", u(1, w(1))), Conditionally(n("n", uw(1)), EmptyStmt(), Connect(n("a", uw(8)), n("b", uw(8)))) ])) ct = DefCircuit("m3", [m1, m2]) assert not check(ct)
def convert_expr(mi: ModuleInst): if mi.module_name not in Context.modules: from .conv_module import convert_module convert_module(mi.packed_module) module = Context.modules[mi.module_name] name = NameGetter.get(mi.id) ref = Reference(name, ports_to_bundle_type(module.ports)) stmts = [ DefInstance(name, mi.module_name), Connect(SubField(ref, 'clock', ClockType()), Reference('clock', ClockType())), Connect(SubField(ref, 'reset', UIntType(Width(1))), Reference('reset', UIntType(Width(1)))) ] Context.expr_obj_id_to_ref[id(mi)] = ref return stmts, ref
def test_connect_basis(): cn = Connect(n("a", uw(8)), n("b", uw(8))) assert check(cn) serialize_stmt_equal(cn, "a <= b") cn = Connect(n("a", sw(8)), n("b", sw(8))) assert check(cn) serialize_stmt_equal(cn, "a <= b") cn = Connect(n("a", uw(8)), u(20, w(8))) assert check(cn) serialize_stmt_equal(cn, 'a <= UInt<8>("h14")') cn = Connect(n("a", sw(8)), s(-20, w(8))) assert check(cn) serialize_stmt_equal(cn, 'a <= SInt<8>("h-14")')
def test_conditionally_basis(): s1 = EmptyStmt() s2 = Connect(n("a", uw(8)), n("b", uw(8))) cn = Conditionally(n("a", uw(1)), s1, s2) assert check(cn) serialize_stmt_equal(cn, "when a :\n" " skip\n" "else :\n" " a <= b") s1 = Block([ Connect(n("a", uw(8)), n("b", uw(8))), Connect(n("c", sw(8)), n("d", sw(8))), ]) s2 = EmptyStmt() cn = Conditionally(u(1, w(1)), s1, s2) assert check(cn) serialize_stmt_equal( cn, 'when UInt<1>("h1") :\n' ' a <= b\n' ' c <= d\n' 'else :\n' ' skip')
def test_block_basis(): blk = Block([EmptyStmt()]) assert check(blk) serialize_stmt_equal(blk, "skip") blk = Block([DefNode("n", u(1, w(1))), Conditionally(n("n", uw(1)), EmptyStmt(), Connect(n("a", uw(8)), n("b", uw(8)))) ]) assert check(blk) serialize_stmt_equal(blk, 'node n = UInt<1>("h1")\n' 'when n :\n' ' skip\n' 'else :\n' ' a <= b')
def convert_stmt(connect: HclConnect): stmts_0, left_ref = convert_expr_by_id(connect.left_expr_id) stmts_1, right_ref = convert_expr_by_id(connect.right_expr_id) return [*stmts_0, *stmts_1, Connect(left_ref, right_ref)]
def test_module_body_wrong(): mod = DefModule("m", [OutputPort("p", uw(8))], Connect(n("p", uw(8)), s(2, w(8)))) assert not check(mod)
def test_module_empty_ports(): mod = DefModule("m", [], Connect(n("p", uw(8)), u(2, w(8)))) assert not check(mod)
def test_circuit_module_wrong(): m1 = DefModule("m1", [OutputPort("p", uw(8))], Connect(n("p", uw(8)), u(2, w(8)))) m2 = DefModule("m2", [], Connect(n("p", uw(8)), u(2, w(8)))) ct = DefCircuit("m1", [m1, m2]) assert not check(ct)