def test_sim_cntr(self): """ Time synchronized monitors (val) and drivers (clk, rst, en) """ # build_dir = "tmp" # if True: with TemporaryDirectory() as build_dir: rtl_sim = self.cntr_build(build_dir) io = rtl_sim.io data = [] def data_collector(): yield Timer(CLK_PERIOD // 2) assert sim.now == CLK_PERIOD // 2 val = io.val while True: yield Timer(CLK_PERIOD) yield WaitCombStable() data.append((sim.now, int(val.read()))) sim = HdlSimulator(rtl_sim) # rtl_sim.set_trace_file("cntr.vcd", -1) procs = [ get_clk_driver(sim, io.clk, CLK_PERIOD), get_rst_driver(sim, io.rst, CLK_PERIOD), get_pull_up_driver(sim, io.en, CLK_PERIOD), data_collector() ] sim.run(CLK_PERIOD * 10.5, extraProcesses=procs) self.assertSequenceEqual(data, REF_DATA)
def test_sim_cntr_sync_pull_up_reset(self): """ Clock dependency on clk * driver of en * monitor of val Simulation step restart due write after reset read """ # build_dir = "tmp" # if True: with TemporaryDirectory() as build_dir: rtl_sim = self.cntr_build(build_dir) io = rtl_sim.io data = [] sim = HdlSimulator(rtl_sim) # rtl_sim.set_trace_file(join(build_dir, "cntr.vcd"), -1) proc = [ get_clk_driver(sim, io.clk, CLK_PERIOD), get_rst_driver(sim, io.rst, CLK_PERIOD), get_sync_pull_up_driver_with_reset(sim, io.en, io.clk, io.rst), get_sync_sig_monitor(sim, io.val, io.clk, io.rst, data) ] sim.run(CLK_PERIOD * 10.5, extraProcesses=proc) self.assertSequenceEqual(data, REF_DATA)