def test_all(self):
file_name = 'Test_CC_test_all.scpi.txt'
test_path = Path('test_output') / file_name
os.makedirs('test_output', exist_ok=True)
transport = FileTransport(str(test_path))
cc = CC('cc', transport, ccio_slots_driving_vsm=[5])
cc.reset()
cc.clear_status()
cc.set_status_questionable_frequency_enable(0x7FFF)
cc.dio0_out_delay(0)
cc.dio0_out_delay(31)
cc.dio8_out_delay(0)
cc.dio8_out_delay(31)
cc.vsm_channel_delay0(0)
cc.vsm_channel_delay0(1)
cc.vsm_channel_delay0(127)
cc.vsm_channel_delay31(0)
cc.vsm_channel_delay31(127)
cc.vsm_rise_delay0(0)
cc.vsm_rise_delay0(48)
cc.vsm_rise_delay31(0)
cc.vsm_rise_delay31(48)
cc.vsm_fall_delay0(0)
cc.vsm_fall_delay0(48)
cc.vsm_fall_delay31(0)
cc.vsm_fall_delay31(48)
cc.debug_marker_in(0, cc.UHFQA_TRIG)
cc.debug_marker_in(0, cc.UHFQA_CW[0])
cc.debug_marker_out(0, cc.UHFQA_TRIG)
cc.debug_marker_out(8, cc.HDAWG_TRIG)
prog = ' stop\n'
cc.sequence_program_assemble(prog)
tmp_file = tempfile.NamedTemporaryFile(mode='w', delete=False)
tmp_file.write(prog)
tmp_file.close() # to allow access to file
# FIXME: disabled because it requires input data, which we do not support yet
#cc.eqasm_program(tmp_file.name)
os.unlink(tmp_file.name)
cc.start()
cc.stop()
transport.close() # to allow access to file
# check results
test_output = test_path.read_text()
golden_path = Path(
pq.__path__[0]
) / 'tests/instrument_drivers/physical_instruments/QuTech/golden' / file_name
golden = golden_path.read_text()
self.assertEqual(test_output, golden)
from pycqed.instrument_drivers.library.Transport import IPTransport
from pycqed.instrument_drivers.physical_instruments.QuTech.CC import CC
# parameter handling
filename = ''
ip = '192.168.0.241'
if len(sys.argv) == 1:
raise ("missing parameter 'filename'")
if len(sys.argv) > 1:
filename = sys.argv[1]
if len(sys.argv) > 2:
ip = sys.argv[2]
log = logging.getLogger(__name__)
log.setLevel(logging.DEBUG)
log.info('connecting to CC')
cc = CC('cc', IPTransport(ip))
cc.init()
if 1:
cc.debug_marker_out(0, cc.UHFQA_TRIG)
cc.debug_marker_out(1, cc.UHFQA_TRIG)
#cc.debug_marker_out(8, cc.HDAWG_TRIG)
log.info(f'uploading {filename} and starting CC')
with open(filename, 'r') as f:
prog = f.read()
cc.assemble_and_start(prog)
p = sqo.off_on(
qubit_idx=qubit_idx, pulse_comb='on',
initialize=False,
platf_cfg=cfg_openql_platform_fn)
print(p.filename)
if 1:
log.debug('connecting to CC')
cc = CC('cc', IPTransport(ip))
cc.reset()
cc.clear_status()
cc.status_preset()
if 1:
cc.debug_marker_out(0, cc.UHFQA_TRIG) # UHF-QA trigger
cc.debug_marker_out(8, cc.HDAWG_TRIG) # HDAWG trigger
log.debug('uploading {}'.format(p.filename))
if 0:
cc.eqasm_program = p.filename
else:
with open(p.filename, 'r') as f:
prog = f.read()
cc.sequence_program_assemble(prog)
err_cnt = cc.get_system_error_count()
for i in range(err_cnt):
print(cc.get_error())
loop: seq_out 0x03FF0000,1 # NB: TRIG=0x00010000, CW[8:0]=0x03FE0000
seq_out 0x0,$wait
jmp @loop
""")
cc.assemble_and_start(cc_prog)
log.debug('calibrating DIO protocol on CC')
if 0: # marker outputs
if 1:
cc.debug_marker_in(
cc_slot_uhfqa0, cc.UHFQA_DV
) # watch DV to check upstream period/frequency
else:
cc.debug_marker_out(
cc_slot_uhfqa0, cc.UHFQA_TRIG
) # watch TRIG to check downstream period/frequency
cc.calibrate_dio_protocol(dio_mask=dio_mask,
expected_sequence=expected_sequence,
port=cc_slot_uhfqa0)
dio_rd_index = cc.debug_get_ccio_reg(cc_slot_uhfqa0,
SYS_ST_OPER_DIO_RD_INDEX)
log.info(
f'DIO calibration condition = 0x{cc.debug_get_ccio_reg(cc_slot_uhfqa0, SYS_ST_QUES_DIOCAL_COND):x} (0=OK)'
)
log.info(f'DIO read index = {dio_rd_index}')
log.info(
f'DIO margin = {cc.debug_get_ccio_reg(cc_slot_uhfqa0, SYS_ST_OPER_DIO_MARGIN)}'
)
if dio_rd_index < 0: