def __init__(self, node, lang=None, resolver=None):
self.node = node
if lang is None:
lang = mod_lang(node)
self.lang = lang
self._impl_parse = None
if 'memoized' in self.node.params:
memnode = self.node.params['memoized']
# TODO: What if hdlmod is a part of different cosim build and
# located at different folder. We should include that folder in the
# path
# TODO: What if hdlmod hasn't been
# generated? This can happen if we only generate a part of the
# design
if memnode in reg['hdlgen/map']:
hdlmod = reg['hdlgen/map'][memnode]
self.resolver = hdlmod.resolver
return
if resolver is not None:
self.resolver = resolver
else:
self.resolver = self.get_resolver()
def wrapped(self):
if mod_lang(self.node.parent) != self.lang:
return True
if self.node is reg['hdl/top'] and self.params:
return True
return False
def __init__(self, node, lang=None, resolver=None):
self.node = node
if lang is None:
lang = mod_lang(node)
self.lang = lang
self._impl_parse = None
if 'memoized' in self.node.params:
memnode = self.node.params['memoized']
# TODO: What if hdlmod hasn't been generated? This can happen if we
# only generate a part of the design
hdlmod = reg['hdlgen/map'][memnode]
self.resolver = hdlmod.resolver
return
if resolver is not None:
self.resolver = resolver
else:
self.resolver = self.get_resolver()
def __init__(self, node, lang=None, resolver=None):
self.node = node
if lang is None:
lang = mod_lang(node)
self.lang = lang
self._impl_parse = None
self.memoized = False
# TODO Investigate which other names create problems
for p in self.node.in_ports + self.node.out_ports:
if p.basename in ['clk', 'rst'] or p.basename in sv_keywords:
raise NameError(f'Unable to compile "{self.node.name}" to HDL, please change port '
f'"{p.basename}" name, it is illegal.')
if 'memoized' in self.node.params:
memnode = self.node.params['memoized']
# TODO: What if hdlmod is a part of different cosim build and
# located at different folder. We should include that folder in the
# path
# TODO: What if hdlmod hasn't been
# generated? This can happen if we only generate a part of the
# design
if memnode in reg['hdlgen/map']:
self.memoized = True
hdlmod = reg['hdlgen/map'][memnode]
self.resolver = hdlmod.resolver
return
if resolver is not None:
self.resolver = resolver
else:
self.resolver = self.get_resolver()
def get_inst(self, template_env, port_map=None):
parent_lang = mod_lang(self.node.parent)
module_name = self.wrap_module_name
if parent_lang == self.lang:
params = self.params
else:
template_env = reg[f'{parent_lang}gen/templenv']
params = {}
if not port_map:
in_port_map = [(port.basename,
self.get_in_port_map_intf_name(port, parent_lang))
for port in self.node.in_ports]
out_port_map = [
(port.basename,
self.get_out_port_map_intf_name(port, parent_lang))
for port in self.node.out_ports
]
port_map = OrderedDict(in_port_map + out_port_map)
sigmap = {}
for s in self.node.meta_kwds['signals']:
sigmap[s.name] = self.node.params['sigmap'].get(s.name, s.name)
context = {
'rst_name': 'rst',
'module_name': rename_ambiguous(module_name, self.lang),
'inst_name': self.inst_name,
'param_map': params,
'port_map': port_map,
'sig_map': sigmap
}
return template_env.snippets.module_inst(**context)
def lang(self):
return mod_lang(self.node)
def parent_lang(self):
return mod_lang(self.node.parent)
def Gear(self, node):
lang = mod_lang(node)
hdlgen = self.hdlgen_map.get(node, None)
if hdlgen is not None:
hdlgen.generate(self.templenv[lang], self.outdir)
