def test_directed_two_inputs(cosim_cls):
verif(drv(t=T_DIN_SEP, seq=[list(range(9)), list(range(5))]),
drv(t=T_CFG, seq=[2, 3]),
f=take(sim_cls=cosim_cls),
ref=take(name='ref_model'))
sim()
def test_mapped_directed(sim_cls, din_delay, cfg_delay, dout_delay, branches):
t_ctrl = Uint[bitw(branches - 1)]
ref = [(i, i) for i in range(branches)]
mapping = {}
for i in range(branches):
mapping[i] = (i + 1) if (i + 1) < branches else 0
ctrl = list(range(branches))
seqs = [[(i - 1) if (i - 1) >= 0 else (branches - 1)]
for i in range(branches)]
drvs = [
drv(t=Uint[s[0] + 1], seq=s) | delay_rng(din_delay, din_delay)
for s in seqs
]
directed(drv(t=t_ctrl, seq=ctrl) | delay_rng(cfg_delay, cfg_delay),
*drvs,
f=mux(mapping=mapping, sim_cls=sim_cls),
delays=[delay_rng(dout_delay, dout_delay)],
ref=ref)
sim()
def test_add():
directed(drv(t=Uint[8], seq=list(range(8))),
drv(t=Uint[8], seq=list(range(8))),
f=add(sim_cls=SimVerilated),
ref=[2 * i for i in range(8)])
sim()
def test_float():
seq = [(1.0, 1.0), (5e-120, 2e-120), (1e+200, 3e+200)]
drv(t=Tuple[Float, Float], seq=seq) \
| sub \
| check(ref=[0.0, 3e-120, -2e+200])
sim()
def test_directed(sim_cls, din_delay, dout_delay):
dut = get_dut(dout_delay)
directed(drv(t=t_din, seq=[list(range(9)), list(range(3))])
| delay_rng(din_delay, din_delay),
drv(t=t_cfg, seq=[2, 3]) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=[[0, 1], [2, 3], [4, 5], [6, 7], [8], [0, 1, 2]],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim(cosim_cls, din_delay, dout_delay):
verif(drv(t=Uint[8], seq=[0]) | delay_rng(din_delay, din_delay),
drv(t=Queue[Uint[8]], seq=[list(range(10))])
| delay_rng(din_delay, din_delay),
f=cart(sim_cls=cosim_cls),
ref=cart(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def get_stim():
cfg_seq = []
din_seq = []
cfg_num = random.randint(2, 10)
for _ in range(cfg_num):
cfg_seq.append(random.randint(1, 10))
din_seq.append(list(range(random.randint(1, 10))))
return [drv(t=t_din, seq=din_seq), drv(t=t_cfg, seq=cfg_seq)]
def test_seq_incompatible_to_t():
drv(t=Uint[2], seq=[(0, 0)]) | shred
with pytest.raises(LogException) as excinfo:
sim()
assert equal_on_nonspace(
str(excinfo.value),
'Cannot convert value "(0, 0)" to type "Uint[2]", in the module "/drv"'
)
def test_replicate_queue(cosim_cls, din_delay, dout_delay):
dut = get_decoupled_dut(dout_delay, replicate_while)
verif(drv(t=Bool, seq=[1, 1, 0] * 5),
drv(t=Queue[Uint[16]], seq=[list(range(5))])
| delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=replicate_while(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_directed(sim_cls):
wr_addr_data = [(i, i * 2) for i in range(4)]
rd_addr = list(range(4))
rd_data = [i * 2 for i in range(4)]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=wr_addr_data),
drv(t=Uint[3], seq=rd_addr) | delay_rng(1, 1),
f=sdp(sim_cls=sim_cls, depth=4, latency=2),
ref=rd_data)
sim()
def test__rmul__(sim_cls):
# Uint __mul__ raises NotImplemented, so __rmul__ of Ufixp needs to be
# invoked
directed(
drv(t=Uint[8], seq=[128]),
drv(t=Ufixp[0, 8], seq=[0.5]),
f=mul,
ref=[64],
)
sim()
def test_fixp_diff_arith(sim_cls):
@gear(hdl={'compile': True})
async def fixp_arith(x: Fixpnumber, y: Fixpnumber) -> Ufixp[6, 9]:
async with gather(x, y) as data:
yield (data[0] + data[1]) + (data[0] + data[1])
directed(drv(t=Ufixp[4, 7], seq=[3.125]),
drv(t=Ufixp[4, 6], seq=[2.25]),
f=fixp_arith(sim_cls=sim_cls),
ref=[Ufixp[6, 9](10.75)])
sim()
def test_q_directed_two_inputs(sim_cls, din_delay, cfg_delay):
seq1 = [list(range(3)) for _ in range(9)]
seq2 = [list(range(6)) for _ in range(5)]
seq = [seq1, seq2]
directed(drv(t=T_QDIN_SEP, seq=seq) | delay_rng(din_delay, din_delay),
drv(t=T_CFG, seq=[2, 3]) | delay_rng(cfg_delay, cfg_delay),
f=take(sim_cls=sim_cls),
ref=[[list(range(3))] * 2, [list(range(6))] * 3])
sim()
def test_sim_prefil(sim_cls):
rd_addr = list(range(4))
mem = {i: 2 * i for i in rd_addr}
rd_data = [mem[i] for i in rd_addr]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=[]),
drv(t=Uint[3], seq=rd_addr),
f=sdp(sim_cls=sim_cls, depth=4, mem=mem),
ref=rd_data)
sim()
def test_directed(
cosim_cls,
wr0_delay,
rd0_delay,
wr1_delay,
rd1_delay,
dout_delay,
depth,
):
def wr0_delay_gen():
for _ in range(depth):
yield 0
while True:
yield wr0_delay
w_addr = 3
w_data = 8
wr_req_t = TWrReq[w_addr, Uint[w_data]]
rd_req_t = Uint[w_addr]
req_t = Union[rd_req_t, wr_req_t]
wr0_req_seq = [(i, i * 2) for i in range(depth)]
wr0_init_seq = [(i, 0) for i in range(depth)]
rd0_req_seq = list(range(depth))
rd1_req_seq = list(range(depth))
wr0_req = drv(t=wr_req_t, seq=wr0_init_seq + wr0_req_seq) \
| delay_gen(f=wr0_delay_gen())
rd0_req = drv(t=Uint[w_addr], seq=rd0_req_seq) \
| delay_gen(f=iter([depth])) \
| delay_rng(0, rd0_delay)
req0 = priority_mux(rd0_req, wr0_req)
req1 = ccat(drv(t=Uint[w_addr], seq=rd1_req_seq) \
| req_t.data \
| delay_gen(f=iter([depth])) \
| delay_rng(0, rd1_delay)
, Bool(False)) | req_t
verif(req0,
req1,
f=tdp(name='dut', sim_cls=cosim_cls, depth=depth),
ref=tdp(depth=depth),
delays=[delay_rng(0, dout_delay),
delay_rng(0, 0)])
sim()
def test_directed(latency):
print(f'Latency: {latency}')
wr_addr_data = [(i, i * 2) for i in range(4)]
rd_addr = list(range(4))
rd_data = [i * 2 for i in range(4)]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=wr_addr_data),
drv(t=Uint[3], seq=rd_addr) | delay_rng(latency, latency),
f=sdp(depth=4, latency=latency),
ref=rd_data)
cosim('/sdp', 'verilator')
sim()
def test_uint_3(cosim_cls, din_delay, dout_delay):
directed(drv(t=Uint[2], seq=[0, 1, 2, 3])
| delay_rng(din_delay[0], din_delay[0]),
drv(t=Uint[3], seq=[4, 5, 6, 7])
| delay_rng(din_delay[1], din_delay[1]),
drv(t=Uint[8], seq=[8, 9, 10, 11])
| delay_rng(din_delay[2], din_delay[2]),
f=ccat(sim_cls=cosim_cls),
ref=[(0, 4, 8), (1, 5, 9), (2, 6, 10), (3, 7, 11)],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_queue_3(cosim_cls, din_delay, dout_delay):
verif(drv(t=Queue[Uint[2]], seq=[[0, 1], [2, 3]])
| delay_rng(din_delay[0], din_delay[0]),
drv(t=Queue[Uint[3]], seq=[[4, 5], [6, 7]])
| delay_rng(din_delay[1], din_delay[1]),
drv(t=Queue[Uint[8]], seq=[[8, 9], [10, 11]])
| delay_rng(din_delay[2], din_delay[2]),
f=ccat(sim_cls=cosim_cls),
ref=ccat(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim_zipsync_both_queue(cosim_cls, din0_delay, din1_delay,
dout0_delay, dout1_delay):
verif(drv(t=Queue[Uint[8], 2], seq=[[list(range(10)) for _ in range(2)]])
| delay_rng(din0_delay, din0_delay),
drv(t=Queue[Uint[8], 2], seq=[[list(range(10)) for _ in range(2)]])
| delay_rng(din1_delay, din1_delay),
f=zip_sync(sim_cls=cosim_cls),
ref=zip_sync(name='ref_model'),
delays=[
delay_rng(dout0_delay, dout0_delay),
delay_rng(dout1_delay, dout1_delay)
])
sim()
def test_tuple_uint_directed(sim_cls, din_delay, cfg_delay, dout_delay):
t_ctrl = Uint[4]
t_din = Tuple[Uint[8], Uint[8], Uint[8]]
dut = get_decoupled_dut(dout_delay, field_mux)
directed(drv(t=t_ctrl, seq=[0, 1, 2])
| delay_rng(cfg_delay, cfg_delay),
drv(t=t_din, seq=[(5, 6, 7), (5, 6, 7), (5, 6, 7)])
| delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=[(5, 0), (6, 1), (7, 2)],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_multiple_arguments_datagear():
TComplex = Tuple[Integer, Integer]
complex_t = Tuple[Uint[8], Uint[8]]
@datagear
def add_real_part_func(x: TComplex, y: TComplex) -> b'x[0]':
return code(x[0] + y[0], type(x[0]))
directed(drv(t=complex_t, seq=[(i, i) for i in range(10)]),
drv(t=complex_t, seq=[(i, i) for i in range(10)]),
f=add_real_part_func(sim_cls=SimVerilated),
ref=[2 * i for i in range(10)])
sim()
def test_tuple_uint_directed(sim_cls, din_delay, ctrl_delay, dout_delay):
from pygears.lib.verif import check
t_ctrl = Uint[4]
t_din = Tuple[Uint[8], Uint[8], Uint[8]]
ctrl = drv(t=t_ctrl, seq=[0, 1, 2]) \
| delay_rng(ctrl_delay, ctrl_delay)
data = drv(t=t_din, seq=[(5, 6, 7), (5, 6, 7), (5, 6, 7)]) \
| delay_rng(din_delay, din_delay)
check(data[ctrl] | delay_rng(dout_delay, dout_delay), ref=[5, 6, 7])
sim()
def test_directed_full_read(latency):
print(f'Latency: {latency}')
depth = 8
mem = list(range(depth))
rd_addr = list(range(8))
rd_data = list(range(8))
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=[]),
drv(t=Uint[3], seq=rd_addr),
f=sdp(depth=8, latency=latency, mem=mem),
ref=rd_data)
cosim('/sdp', 'verilator')
sim()
def test_directed(sim_cls, din_delay, dout_delay):
dut = get_dut(dout_delay)
directed(drv(t=T_DIN, seq=[list(range(9)), list(range(3))])
| delay_rng(din_delay, din_delay),
drv(t=T_DIN, seq=[list(range(9)), list(range(3))])
| delay_rng(din_delay, din_delay),
drv(t=T_DIN, seq=[list(range(9)), list(range(3))])
| delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=[[[0, 1, 2, 3, 4, 5, 6, 7, 8], [0, 1, 2, 3, 4, 5, 6, 7, 8],
[0, 1, 2, 3, 4, 5, 6, 7, 8]],
[[0, 1, 2], [0, 1, 2], [0, 1, 2]]],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def filt_by_test(din_t, seq, sel, sim_cls):
din_seq, ctrl_seq = zip(*seq)
din_drv = drv(t=din_t, seq=din_seq)
ctrl_drv = drv(t=Uint[2], seq=ctrl_seq)
@datagear
def cond(ctrl: Uint, din) -> Bool:
return ctrl == sel
directed(
din_drv,
f=filt(f=cond(ctrl_drv), sim_cls=sim_cls),
ref=[val for (val, ctrl) in zip(din_seq, ctrl_seq) if (ctrl == sel)])
sim()
def test_basic(cosim_cls):
seq_op1 = [1, 2, 3]
seq_op2 = [2, 2, 2]
@gear
def eq_wrap(op1, op2):
return op1 == op2
verif(drv(t=Uint[4], seq=seq_op1),
drv(t=Uint[4], seq=seq_op2),
f=eq_wrap(sim_cls=cosim_cls),
ref=eq(name='ref_model'))
sim(check_activity=False)
def test_random_constrained():
skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST')
cnt = 5
# cons.append(randomize(T_CFG, 'cfg', cons=['cfg == 2']))
stim = []
stim.append(drv(t=T_DIN_SEP, seq=randomize(T_DIN_SEP, 'din', cnt=cnt)))
stim.append(
drv(t=T_CFG, seq=randomize(T_CFG, 'cfg', cons=['cfg < 20', 'cfg > 0'], cnt=cnt)))
verif(*stim, f=clip, ref=clip(name='ref_model'))
cosim('/clip', 'xsim', run=False)
sim()
def test_directed_3in(cosim_cls, din_delay, dout_delay):
t_deal = Queue[Uint[16], 3]
num = 3
lvl = 2
seq = [[[list(range(3)), list(range(5))],
[list(range(1)), list(range(4)),
list(range(4)), list(range(8))]],
[[list(range(3)), list(range(5)), list(range(1))], [list(range(1)),
list(range(8))], [list(range(4))]],
[[list(range(3)), list(range(1))], [list(range(1))]]]
ref0 = [seq[0][0], seq[1][0], seq[2][0]]
ref1 = [seq[0][1], seq[1][1], seq[2][1]]
ref2 = [seq[1][2]]
ref = [ref0, ref1, ref2]
dout_dly = [delay_rng(dout_delay, dout_delay)] * num
dut = get_dut(dout_delay)
directed(drv(t=t_deal, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls, lvl=lvl, num=num),
ref=ref,
delays=dout_dly)
sim()
def test_directed_dout_throtle(latency):
print(f'Latency: {latency}')
depth = 8
mem = list(range(depth))
rd_addr = list(range(8))
rd_data = list(range(8))
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=[]),
drv(t=Uint[3], seq=rd_addr),
f=sdp(depth=8, latency=latency, mem=mem),
delays=[delay_rng(4, 4)],
ref=rd_data)
cosim('/sdp', 'verilator')
sim()
def test_basic(cosim_cls):
seq_op1 = [1, 2, 3]
seq_op2 = [2, 2, 2]
@gear
def xor_wrap(op1, op2):
return op1 ^ op2
verif(
drv(t=Uint[4], seq=seq_op1),
drv(t=Uint[4], seq=seq_op2),
f=xor_wrap(sim_cls=cosim_cls),
ref=xor(name='ref_model'))
sim()