def test_directed(sim_cls, din_delay, dout_delay):
seq = []
tmp = []
for i in range(9):
tmp.append((i, 2))
seq.append(tmp)
tmp = []
for i in range(5):
tmp.append((i, 3))
seq.append(tmp)
dut = get_dut(dout_delay)
directed(
drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=[[0, 1], list(range(2, 9)),
list(range(3)), list(range(3, 5))],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_leave_branched(din_delay, dout_delay):
@gear
async def test(din: Bool) -> Bool:
c = Bool(True)
d = True
while c:
async with din as c:
if c:
d = 0
else:
d = 1
yield d
verif(drv(t=Bool, seq=[True, False, False, True]) | delay_rng(din_delay, din_delay),
f=test(name='dut'),
ref=test,
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim()
def test_async_over_if_over_async(lang, din_delay, dout_delay):
@gear
async def test(sel: Bool, din0: Uint, din1: Uint) -> b'max(din0, din1)':
async with sel as s:
if s:
async with din1 as d1:
yield d1
else:
async with din0 as d0:
yield d0
directed(drv(t=Bool, seq=[0, 1, 0, 1, 0, 1, 0, 1]),
drv(t=Uint[4], seq=list(range(4)))
| delay_rng(din_delay, din_delay),
drv(t=Uint[4], seq=list(range(4, 8)))
| delay_rng(din_delay, din_delay),
f=test,
ref=[0, 4, 1, 5, 2, 6, 3, 7])
cosim('/test', 'verilator', lang=lang)
sim(check_activity=False)
def test_outsig(lang):
@gear(signals=[InSig('clk', 1),
InSig('rst', 1),
OutSig('flush', 1)],
hdl={'compile': True})
async def local_rst(din):
sig = module().signals['flush']
sig.write(0)
async with din as d:
if d:
sig.write(1)
else:
sig.write(0)
@gear
def hier(din: Bool):
din | local_rst
drv(t=Bool, seq=[False, True]) | hier
cosim('/hier', 'verilator', lang=lang)
sim()
def test_yield_after_loop_reg_scope(din_delay, dout_delay):
@gear
async def test(din: Bool) -> Uint[4]:
a = Uint[3](0)
c = True
while c:
async with din as c:
yield a
a += 1
yield a + 2
verif(drv(t=Bool, seq=[True, False, False, True])
| delay_rng(din_delay, din_delay),
f=test(name='dut'),
ref=test,
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim()
def test_cond_nested_loop_multistate(din_delay, dout_delay):
@gear
async def test(din: Queue[Bool]) -> Uint[4]:
a = Uint[4](0)
while a < 4:
if a < 2:
async for d in din:
yield a
# Influences above condition, but should not make a
# difference while loop is running
a += 1
a += 1
verif(drv(t=Queue[Bool], seq=[[True] * 4, [True], [True], [True] * 4])
| delay_rng(din_delay, din_delay),
f=test(name='dut'),
ref=test,
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim()
def test_double_loop_seq(din_delay, dout_delay):
@gear
async def test(din: Uint[4]) -> Uint[4]:
c = Uint[4](0)
while c[:1] == 0:
async with din as c:
yield c
c = Uint[4](0)
while c[:1] == 0:
async with din as c:
yield code(2 * c, Uint[4])
verif(drv(t=Uint[4], seq=[1, 2, 3, 4, 1, 2, 3, 4])
| delay_rng(din_delay, din_delay),
f=test(name='dut'),
ref=test,
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim()
def comp_pid_lti_comb_ref(Kp, Ki, Kd, Nfilt):
plant = tf([1], [1, 10, 20])
config['sim/clk_freq'] = 1000
seq = [0.] * 2 + [1.] * config['sim/clk_freq']
set_point = drv(t=Float, seq=seq)
plant_out = set_point \
| pid_lti_comb(Kp=Kp, Ki=Ki, Kd=Kd, Nfilt=Nfilt, plant=plant)
plant_out | scope(title="Plant Output")
ref_out = set_point \
| pid_lti_feedback(Kp=Kp, Ki=Ki, Kd=Kd, Nfilt=Nfilt, plant=plant)
ref_out | scope(title="Continuous Reference")
report = []
scoreboard(plant_out, ref_out, report=report, tolerance=2e-2)
sim(timeout=len(seq))
def test_queue_directed(sim_cls, din_delay, dout_delay, cfg_delay):
t_din = Queue[Uint[16]]
t_cfg = Uint[16]
dut = get_dut(dout_delay)
directed(drv(t=t_din,
seq=[
list(range(5)),
list(range(3)),
list(range(2)),
list(range(3)),
list(range(8))
])
| delay_rng(din_delay, din_delay),
drv(t=t_cfg, seq=[2, 3]) | delay_rng(cfg_delay, cfg_delay),
f=dut(sim_cls=sim_cls),
ref=[[list(range(5)), list(range(3))],
[list(range(2)),
list(range(3)),
list(range(8))]],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_addi_verilator():
test_instr = ADDI.replace(imm=-1233, rd=1, rs1=1)
reg_file_init = {1: -1}
spike_reg_file_start, spike_reg_file_end = spike_instr_test.run_all(
[test_instr], outdir='build', reg_file_init=reg_file_init)
reg_file_mem = riscv_instr_seq_env(instr_seq=[test_instr],
xlen=32,
reg_file_mem=dict(
enumerate(spike_reg_file_start)))
find('/riscv').params['sim_cls'] = SimVerilated
sim("build")
print(
f'Resulting value of the register x1: {cast(reg_file_mem[1], Int[32])}'
)
for reg_id, reg_value in reg_file_mem.items():
assert spike_reg_file_end[reg_id] == reg_value
def test_addi():
test_instr = ADDI.replace(imm=-1233, rd=1, rs1=1)
reg_file_init = {1: -1}
spike_reg_file_start, spike_reg_file_end = spike_instr_test.run_all(
[test_instr], outdir='build', reg_file_init=reg_file_init)
reg_file_mem = riscv_instr_seq_env(instr_seq=[test_instr],
xlen=32,
reg_file_mem=dict(
enumerate(spike_reg_file_start)))
from pygears.sim.extens.vcd import VCD
sim(extens=[VCD], outdir='/tools/home/tmp')
print(
f'Resulting value of the register x1: {cast(reg_file_mem[1], Int[32])}'
)
for reg_id, reg_value in reg_file_mem.items():
assert spike_reg_file_end[reg_id] == reg_value
def test_open_rand_cons():
skip_ifndef('VERILATOR_ROOT', 'SCV_HOME', 'RANDOM_TEST')
cnt = 5
cons = []
# TODO : queue constraints not yet supported in SCVRand
# cons.append(randomize(t_din, 'din', eot_cons=['data_size == 20']))
cons.append(randomize(t_cfg, 'cfg', cons=['cfg < 20', 'cfg > 0']))
stim = []
din_seq = []
for i in range(cnt):
din_seq.append(list(range(random.randint(1, 10))))
stim.append(drv(t=t_din, seq=din_seq))
# stim.append(drv(t=t_din, seq=rand_seq('din', cnt)))
stim.append(drv(t=t_cfg, seq=rand_seq('cfg', cnt)))
verif(*stim, f=chop(sim_cls=SimVerilated), ref=chop(name='ref_model'))
sim(extens=[partial(SCVRand, cons=cons)])
def test_iir_direct(tmpdir, impl):
config['sim/clk_freq'] = 100000
t = list(range(config['sim/clk_freq']))[0:100]
fs = config['sim/clk_freq']
f1 = 1000
f2 = 70000
seq = []
for n in t:
seq.append(1 * sin(2 * pi * f1 / fs * n) +
0.1 * sin(2 * pi * f2 / fs * n))
sos = signal.butter(N=5,
Wn=30000 / 100000,
btype='lowpass',
analog=False,
output='sos')
a, b = [], []
for s in sos:
b.append(list(s[0:3]))
a.append(list(s[3:]))
t_coef = Fixp[2, 32]
b = [[t_coef(coef) for coef in section] for section in b]
a = [[t_coef(coef) for coef in section] for section in a]
gain = [Fixp[1, 23](1)] * len(b)
ref = signal.sosfilt(sos, seq)
fp_ref = [float(r) for r in ref]
drv(t=Fixp[5, 24], seq=seq) \
| impl(a=a,b=b, gain=gain, ogain=1) \
| Float \
| check(ref=fp_ref[:len(seq)], cmp=lambda x, y: abs(x-y) < 1e-3)
sim(tmpdir, check_activity=False)
def test_unfold_array(lang):
@gear
async def test(din: Array[Maybe, 'num']) -> b'Array[Uint[bitw(num-1)], num]':
num = len(din.dtype)
TIndex = Uint[bitw(num - 1)]
data = Array[TIndex, num]()
async with din as d:
cnt = TIndex(0)
for i in range(num):
data[i] = cnt
if d[i].ctrl:
cnt += 1
yield data
TMaybe = Maybe[Uint[4]]
seq = [
(1, 2, 3, 4),
(2, None, None, 3),
(None, None, 1, 2),
(1, 2, 3, None),
(None, None, None, None),
]
seq = [[TMaybe() if v is None else TMaybe.some(v) for v in arv] for arv in seq]
ref = [
(0, 1, 2, 3),
(0, 1, 1, 1),
(0, 0, 0, 1),
(0, 1, 2, 3),
(0, 0, 0, 0),
]
directed(drv(t=Array[TMaybe, 4], seq=seq), f=test, ref=ref)
cosim('/test', 'verilator', lang=lang)
sim()
def test_hier_level1():
reg['gear/memoize'] = True
@gear
def test(a, b):
return a + b
@gear
def top(a, b, c, d):
t0 = test(a, b)
t1 = test(c, d)
return t0 + t1
directed(drv(t=Uint[4], seq=[1]),
drv(t=Uint[4], seq=[2]),
drv(t=Uint[4], seq=[3]),
drv(t=Uint[4], seq=[4]),
f=top,
ref=[10])
assert check_memoized('/top/test1')
sim()
def test_complex1(din_delay, dout_delay):
@gear
async def test(din: Queue, is_done) -> b'(din, din)':
first_elem = True
for_shred = False
async for m, last in din:
if for_shred:
yield None, None
elif first_elem:
async with is_done as med_found:
if med_found:
for_shred = True
yield None, (m, last)
else:
first_elem = False
yield (m, last), None
elif not last:
first_elem = False
yield (m, last), None
else:
first_elem = True
yield (m, last), None
t = Queue[Uint[4], 1]
verif(drv(t=t, seq=[list(range(5))] * 3) | delay_rng(din_delay, din_delay),
drv(t=Bool, seq=[False, False, True])
| delay_rng(din_delay * 2, din_delay * 2),
f=test(name='dut'),
ref=test,
delays=[
delay_rng(dout_delay, dout_delay),
delay_rng(dout_delay, dout_delay)
])
cosim('/dut', 'verilator')
sim()
def comp_pid_pg_comb_lti_comb(Kp, Ki, Kd, Nfilt):
plant = tf([1], [1, 10, 20])
config['sim/clk_freq'] = 1000
seq = [0.] * 2 + [1.] * config['sim/clk_freq']
set_point = drv(t=Float, seq=seq)
plant_out = set_point \
| pid_pg_comb(Kp=Kp, Ki=Ki, Kd=Kd, Nfilt=Nfilt, plant=plant)
find('/pid_pg_comb/pid.x').producer | scope(title="PID Input")
find('/pid_pg_comb/pid.dout').consumer | scope(title="PID Output")
plant_out | scope(title="Plant Output")
ref_out = set_point \
| pid_lti_comb(Kp=Kp, Ki=Ki, Kd=Kd, Nfilt=Nfilt, plant=plant)
ref_out | scope(title="Continuous Reference")
report = []
scoreboard(plant_out, ref_out, report=report, tolerance=2e-2)
sim(timeout=len(seq))
def test_optional_loop_assign_complex(din_delay, dout_delay):
@gear
async def test(din: Queue) -> Uint[8]:
max_el = din.dtype.data.min
max_idx = Uint[8](0)
cnt = Uint[8](0)
async for d, eot in din:
if d >= max_el:
max_el = d
max_idx = cnt
cnt += 1
yield max_idx
seq = list(range(4)) + list(range(4, 0, -1))
verif(drv(t=Queue[Uint[4]], seq=[seq, seq])
| delay_rng(din_delay, din_delay),
f=test(name='dut'),
ref=test,
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim()
def test_start_stop(sim_cls):
directed(drv(t=Tuple[Uint[2], Uint[4]], seq=[(2, 10)]),
f=qrange(sim_cls=sim_cls),
ref=[list(range(2, 10))])
sim()
def test_random(sim_cls):
skip_ifndef('RANDOM_TEST')
stim = get_stim()
verif(*stim, f=chop(sim_cls=sim_cls), ref=chop(name='ref_model'))
sim()
from cascade_classifier.python_utils.frame import FrameClass
from cascade_classifier.pygears_impl.design.ii_gen import ii_gen, sii_gen
from pygears.typing import Queue, Uint
from pygears.lib.verif import directed
from pygears.sim import sim
from pygears.lib.verif import drv
from pygears.sim.modules.verilator import SimVerilated
img_fn = '../../../datasets/proba.pgm'
img = FrameClass(img_fn, (5, 5))
seq = [img.img]
ref_ii = [img.ii.tolist()]
ref_sii = [img.sii.tolist()]
directed(
drv(t=Queue[Uint[8], 2], seq=seq),
f=ii_gen(frame_size=img.frame_size, sim_cls=SimVerilated),
ref=ref_ii)
directed(
drv(t=Queue[Uint[8], 2], seq=seq),
f=sii_gen(frame_size=img.frame_size, sim_cls=SimVerilated),
ref=ref_sii)
sim("build/")
def test_lvl2(cosim_cls):
directed(drv(t=Queue[Uint[4], 2], seq=[[[0, 1], [2, 3]]]),
f=sot_queue(sim_cls=cosim_cls),
ref=[(0, 3), (1, 2), (2, 1), (3, 0)])
sim()
try:
if test_sel == 0:
drv(t=b_coef_type, seq=x) \
| fir_direct(b=b_coef_fixp) \
| Float \
| check(ref=ref[:len(x)], cmp=lambda x, y: abs(x-y) < 1e-3)
if enable_svgen:
cosim('fir_direct',
'verilator',
outdir='../../outputs/fir/rtl',
timeout=1000)
else:
drv(t=b_coef_type, seq=x) \
| fir_transposed(b=b_coef_fixp) \
| Float \
| check(ref=ref[:len(x)], cmp=lambda x, y: abs(x-y) < 1e-3)
if enable_svgen:
cosim('fir_transposed',
'verilator',
outdir='../../outputs/fir/rtl',
timeout=1000)
sim('../../outputs/fir/')
log.info("\033[92m //==== PASS ====// \033[90m")
except:
# printing stack trace
traceback.print_exc()
log.info("\033[91m //==== FAILED ====// \033[90m")
def test_qmax(sim_cls):
seq = [list(range(-20, 24, 4))]
directed(drv(t=Queue[Int[8]], seq=seq), f=qmax, ref=[max(s) for s in seq])
sim()
def test_stop_unsigned(sim_cls):
directed(drv(t=Uint[4], seq=[4]),
f=qrange(sim_cls=sim_cls),
ref=[list(range(4))])
sim()
def test_start_stop_step_combined(sim_cls):
res = []
qrange((0, 8, 1), sim_cls=sim_cls) | collect(result=res)
sim(timeout=16)
assert res == [(i, i == 7) for i in range(8)] * 2
def test_start_stop_combined(sim_cls):
directed(drv(t=Tuple[Int[2], Uint[4]], seq=[(-2, 7)]),
f=qrange(sim_cls=sim_cls),
ref=[list(range(-2, 7))])
sim()
def test_sin_signed(sim_cls):
drv(t=Fixp[2, 16], seq=[math.pi/12*i for i in range(-6, 5)]) \
| funclut(f=math.sin, sim_cls=sim_cls) \
| check(ref=[math.sin(math.pi/12*i) for i in range(-6, 5)], cmp=lambda x, y: abs(x-y) <= 1)
sim()
def test_sqrt(sim_cls):
drv(t=Ufixp[8, 8], seq=[0, 4, 64, 121]) \
| funclut(f=math.sqrt, precision=4, sim_cls=sim_cls) \
| check(ref=[0, 2, 8, 11])
sim()
def test_start_stop_inclusive(sim_cls):
directed(drv(t=Tuple[Uint[2], Uint[4]], seq=[(2, 10)]),
f=qrange(inclusive=True, sim_cls=sim_cls),
ref=[list(range(2, 11))])
sim()
