3)),
'input_en1': (REG_ENABLE, to_reg_unsigned(0, 1), from_reg_unsigned(0, 1)),
'input_en2': (REG_ENABLE, to_reg_unsigned(1, 1), from_reg_unsigned(1, 1)),
'output_en1': (REG_ENABLE, to_reg_unsigned(2, 1), from_reg_unsigned(2, 1)),
'output_en2': (REG_ENABLE, to_reg_unsigned(3, 1), from_reg_unsigned(3, 1)),
'matrixscale_ch1_ch1':
(REG_CH0_CH0GAIN,
to_reg_signed(0,
16,
xform=lambda obj, x: int(
round(x * (_ADC_DEFAULT_CALIBRATION /
(10.0 if obj.get_frontend(1)[1] else 1.0)) *
obj._adc_gains()[0] * 2.0**10))),
from_reg_signed(
0,
16,
xform=lambda obj, x: x * (
(10.0 if obj.get_frontend(1)[1] else 1.0
) / _ADC_DEFAULT_CALIBRATION) / obj._adc_gains()[0] / 2.0**10)),
'matrixscale_ch1_ch2':
(REG_CH0_CH1GAIN,
to_reg_signed(0,
16,
xform=lambda obj, x: int(
round(x * (_ADC_DEFAULT_CALIBRATION /
(10.0 if obj.get_frontend(2)[1] else 1.0)) *
obj._adc_gains()[1] * 2.0**10))),
from_reg_signed(
0,
16,
xform=lambda obj, x: x * (
(10.0 if obj.get_frontend(2)[1] else 1.0
if monitor_ch == 'a':
self.monitor_a = source
self.monitor_select0 = monitor_sources[source]
elif monitor_ch == 'b':
self.monitor_b = source
self.monitor_select1 = monitor_sources[source]
else:
raise ValueOutOfRangeException("Invalid channel %d", monitor_ch)
_llb_reg_hdl = {
'_fast_scale':
(REG_LLB_GAINS_SCALING, to_reg_signed(0,
16,
xform=lambda obj, x: x * 2**14),
from_reg_signed(0, 16, xform=lambda obj, x: x / 2**14)),
'_slow_scale': (REG_LLB_GAINS_SCALING,
to_reg_signed(16, 16, xform=lambda obj, x: x * 2**14),
from_reg_signed(16, 16, xform=lambda obj, x: x / 2**14)),
'_aux_scale':
(REG_LLB_AUX_SCALE, to_reg_signed(0, 16, xform=lambda obj, x: x * 2**14),
from_reg_signed(0, 16, xform=lambda obj, x: x / 2**14)),
'scan_amplitude': (REG_LLB_SCAN_SCALE,
to_reg_signed(0, 16, xform=lambda obj, x: x * 2**14),
from_reg_signed(0, 16, xform=lambda obj, x: x / 2**14)),
'fast_scan_enable': (REG_LLB_SCAN_CTRL, to_reg_unsigned(0, 1),
from_reg_unsigned(0, 1)),
'slow_scan_enable': (REG_LLB_SCAN_CTRL, to_reg_unsigned(1, 1),
from_reg_unsigned(1, 1)),
'lo_phase_offset': (REG_LLB_LO_PHASE_OFFSET, to_reg_unsigned(0, 28),
from_reg_unsigned(0, 28)),
self.set_frontend(1, fiftyr=True, atten=True, ac=True)
self.set_frontend(2, fiftyr=True, atten=True, ac=True)
self.en_in_ch1 = True
self.en_in_ch2 = True
def _on_sync_regs(self):
self.timestep = 1.0 / (_PM_UPDATE_RATE / self.output_decimation)
_pm_reg_handlers = {
'init_freq_ch1':
((REG_PM_INITF1_H, REG_PM_INITF1_L),
to_reg_unsigned(0, 48, xform=lambda obj, f: f * _PM_FREQSCALE),
from_reg_unsigned(0, 48, xform=lambda obj, f: f / _PM_FREQSCALE)),
'init_freq_ch2':
((REG_PM_INITF2_H, REG_PM_INITF2_L),
to_reg_unsigned(0, 48, xform=lambda obj, f: f * _PM_FREQSCALE),
from_reg_unsigned(0, 48, xform=lambda obj, f: f / _PM_FREQSCALE)),
'output_decimation': (REG_PM_OUTDEC, to_reg_unsigned(0, 17),
from_reg_unsigned(0, 17)),
'output_shift': (REG_PM_OUTSHIFT, to_reg_unsigned(17, 5),
from_reg_unsigned(17, 5)),
'bandwidth_ch1': (REG_PM_BW1, to_reg_signed(0, 5, xform=lambda obj, b: b),
from_reg_signed(0, 5, xform=lambda obj, b: b)),
'bandwidth_ch2': (REG_PM_BW2, to_reg_signed(0, 5, xform=lambda obj, b: b),
from_reg_signed(0, 5, xform=lambda obj, b: b)),
'autoacquire_ch1': (REG_PM_AUTOA1, to_reg_bool(0), from_reg_bool(0)),
'autoacquire_ch2': (REG_PM_AUTOA2, to_reg_bool(0), from_reg_bool(0))
}
'loop_sweep': (REG_FRA_ENABLES, to_reg_bool(0), from_reg_bool(0)),
'single_sweep': (REG_FRA_ENABLES, to_reg_bool(1), from_reg_bool(1)),
'sweep_reset': (REG_FRA_ENABLES, to_reg_bool(2), from_reg_bool(2)),
'channel1_en': (REG_FRA_ENABLES, to_reg_bool(3), from_reg_bool(3)),
'channel2_en': (REG_FRA_ENABLES, to_reg_bool(4), from_reg_bool(4)),
'adc1_en': (REG_FRA_ENABLES, to_reg_bool(5), from_reg_bool(5)),
'adc2_en': (REG_FRA_ENABLES, to_reg_bool(6), from_reg_bool(6)),
'dac1_en': (REG_FRA_ENABLES, to_reg_bool(7), from_reg_bool(7)),
'dac2_en': (REG_FRA_ENABLES, to_reg_bool(8), from_reg_bool(8)),
'sweep_freq_min':
((REG_FRA_SWEEP_FREQ_MIN_H, REG_FRA_SWEEP_FREQ_MIN_L),
to_reg_unsigned(0, 48, xform=lambda obj, f: f * _FRA_FREQ_SCALE),
from_reg_unsigned(0, 48, xform=lambda obj, f: f / _FRA_FREQ_SCALE)),
'sweep_freq_delta':
((REG_FRA_SWEEP_FREQ_DELTA_H, REG_FRA_SWEEP_FREQ_DELTA_L),
to_reg_signed(0, 48), from_reg_signed(0, 48)),
'log_en': (REG_FRA_LOG_EN, to_reg_bool(0), from_reg_bool(0)),
'sweep_length': (REG_FRA_SWEEP_LENGTH, to_reg_unsigned(0, 10),
from_reg_unsigned(0, 10)),
'settling_time':
(REG_FRA_HOLD_OFF_L,
to_reg_unsigned(0, 32, xform=lambda obj, t: t * _FRA_FPGA_CLOCK),
from_reg_unsigned(0, 32, xform=lambda obj, t: t / _FRA_FPGA_CLOCK)),
'averaging_time':
(REG_FRA_AVERAGE_TIME,
to_reg_unsigned(0, 32, xform=lambda obj, t: t * _FRA_FPGA_CLOCK),
from_reg_unsigned(0, 32, xform=lambda obj, t: t / _FRA_FPGA_CLOCK)),
'sweep_amplitude_ch1':
(REG_FRA_SWEEP_AMP_MULT,
to_reg_unsigned(0, 16, xform=lambda obj, a: a / obj._dac_gains()[0]),
from_reg_unsigned(0, 16, xform=lambda obj, a: a * obj._dac_gains()[0])),
_ARB_MODE_125, _ARB_MODE_250, _ARB_MODE_500,
_ARB_MODE_1000
]), from_reg_unsigned(2, 2)),
'interpolation1': (REG_ARB_SETTINGS1, to_reg_bool(4), from_reg_bool(4)),
'trig_source1': (REG_ARB_SETTINGS1,
to_reg_unsigned(5,
5,
allow_set=[
_ARB_TRIG_SRC_CH1, _ARB_TRIG_SRC_CH2,
_ARB_TRIG_SRC_EXT
]), from_reg_unsigned(5, 5)),
'lut_length1':
(REG_ARB_LUT_LENGTH1, to_reg_unsigned(0, 16), from_reg_unsigned(0, 16)),
'dead_value1': (REG_ARB_LUT_LENGTH1,
to_reg_signed(16, 16, xform=lambda obj, r: r * (2.0**15)),
from_reg_signed(16, 16, xform=lambda obj, r: r /
(2.0**15))),
'amplitude1':
(REG_ARB_AMPLITUDE1,
to_reg_signed(0, 18, xform=lambda obj, r: r / obj._dac_gains()[0]),
from_reg_signed(0, 18, xform=lambda obj, r: r * obj._dac_gains()[0])),
'offset1': (REG_ARB_OFFSET1,
to_reg_signed(0,
16,
xform=lambda obj, r: r / obj._dac_gains()[0]),
from_reg_signed(0,
16,
xform=lambda obj, r: r * obj._dac_gains()[0])),
'enable2': (REG_ARB_SETTINGS2, to_reg_bool(0), from_reg_bool(0)),
'phase_rst2': (REG_ARB_SETTINGS2, to_reg_bool(1), from_reg_bool(1)),
'mode2': (REG_ARB_SETTINGS2,
to_reg_unsigned(2,
'ch1_pid2_den': (REG_PID_ENABLES, to_reg_bool(21), from_reg_bool(21)),
'ch2_pid1_den': (REG_PID_ENABLES, to_reg_bool(22), from_reg_bool(22)),
'ch2_pid2_den': (REG_PID_ENABLES, to_reg_bool(23), from_reg_bool(23)),
'ch1_output_en': (REG_PID_ENABLES, to_reg_bool(24), from_reg_bool(24)),
'ch2_output_en': (REG_PID_ENABLES, to_reg_bool(25), from_reg_bool(25)),
'ch1_input_en': (REG_PID_MONSELECT, to_reg_bool(6), from_reg_bool(6)),
'ch2_input_en': (REG_PID_MONSELECT, to_reg_bool(7), from_reg_bool(7)),
'ch1_input_light': (REG_PID_MONSELECT, to_reg_bool(8), from_reg_bool(8)),
'ch2_input_light': (REG_PID_MONSELECT, to_reg_bool(9), from_reg_bool(9)),
'ch1_ch1_gain':
((REG_PID_CH0_CH0GAIN_MSB, REG_PID_CH0_CH0GAIN_LSB),
to_reg_signed(24,
16,
xform=lambda obj, x: x * 2.0**8 * obj._adc_gains()[0]),
from_reg_signed(24,
16,
xform=lambda obj, x: x / 2.0**8 / obj._adc_gains()[0])),
'ch1_ch2_gain':
(REG_PID_CH0_CH1GAIN,
to_reg_signed(0,
16,
xform=lambda obj, x: x * 2.0**8 * obj._adc_gains()[0]),
from_reg_signed(0,
16,
xform=lambda obj, x: x / 2.0**8 / obj._adc_gains()[0])),
'ch2_ch1_gain':
((REG_PID_CH1_CH0GAIN_MSB, REG_PID_CH1_CH0GAIN_LSB),
to_reg_signed(24,
16,
xform=lambda obj, x: x * 2.0**8 * obj._adc_gains()[1]),
from_reg_signed(24,
'ch1_pid1_int_dc_pole':
(REG_LIA_ENABLES, to_reg_bool(16), from_reg_bool(16)),
'ch2_signal_en': (REG_LIA_ENABLES, to_reg_bool(17), from_reg_bool(17)),
'ext_demod': (REG_LIA_ENABLES, to_reg_bool(18), from_reg_bool(18)),
'lo_PLL': (REG_LIA_ENABLES, to_reg_bool(19), from_reg_bool(19)),
'filt_bypass1': (REG_LIA_ENABLES, to_reg_bool(21), from_reg_bool(21)),
'filt_bypass2': (REG_LIA_ENABLES, to_reg_bool(22), from_reg_bool(22)),
'pid_ch_select': (REG_LIA_ENABLES, to_reg_bool(23), from_reg_bool(23)),
'aux_select':
(REG_LIA_ENABLES, to_reg_unsigned(26, 2), from_reg_unsigned(26, 2)),
'input_gain_select': (REG_LIA_ENABLES, to_reg_unsigned(28, 2),
from_reg_unsigned(28, 2)),
'ch1_pid1_in_offset':
(REG_LIA_IN_OFFSET1,
to_reg_signed(16, 16, xform=lambda obj, x: x / obj._dac_gains()[0]),
from_reg_signed(16, 16, xform=lambda obj, x: x * obj._dac_gains()[0])),
'ch1_pid1_out_offset':
(REG_LIA_OUT_OFFSET1,
to_reg_signed(16, 16, xform=lambda obj, x: x / obj._dac_gains()[0]),
from_reg_signed(16, 16, xform=lambda obj, x: x * obj._dac_gains()[0])),
'main_offset':
(REG_LIA_OUT_OFFSET1,
to_reg_signed(0, 16, xform=lambda obj, x: x / obj._dac_gains()[0]),
from_reg_signed(0, 16, xform=lambda obj, x: x * obj._dac_gains()[0])),
'lpf_pidgain': (REG_LIA_PIDGAIN1,
to_reg_signed(0, 32, xform=lambda obj, x: x * 2**15),
from_reg_signed(0, 32, xform=lambda obj, x: x / 2**15)),
'ch1_pid1_pidgain': (REG_LIA_PIDGAIN2,
to_reg_signed(0, 32, xform=lambda obj, x: x),
from_reg_signed(0, 32, xform=lambda obj, x: x)),
'lpf_int_i_gain':
def level(self):
r = self.reg_base + Trigger._REG_LEVEL
return self._instr._accessor_get(r, from_reg_signed(0, 32))
def output_offset(self):
r = self.reg_base + PID._REG_OUT_OFFSET
return self._instr._accessor_get(r, from_reg_signed(0, 16))
def i_fb(self):
r = self.reg_base + PID._REG_I_FB
return self._instr._accessor_get(
r, from_reg_signed(0, 25, xform=lambda obj, x: x / (2.0**24 - 1)))