def construct(s):
s.src = TestSource(Bits32, [2, 1, 0, 2, 1, 0])
s.sink = TestSink(
Bits32,
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[Wire(Bits32) for _ in range(2)] for _ in range(2)]
@s.update
def up_from_src():
s.wire[0][0] = s.src.out
s.wire[0][1] = s.src.out + 1
s.reg = Wire(Bits32)
@s.update_ff
def up_reg():
s.reg <<= s.wire[0][0] + s.wire[0][1]
@s.update
def upA():
for i in range(2):
s.wire[1][i] = s.reg + i
@s.update
def up_to_sink():
s.sink.in_ = s.wire[1][0] + s.wire[1][1]
def construct(s):
s.src = TestSource(Bits32, [2, 1, 0, 2, 1, 0])
s.sink = TestSink(
Bits32,
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[Wire(Bits32) for _ in range(2)] for _ in range(2)]
connect(s.wire[0][0], s.src.out)
@update
def up_from_src():
s.wire[0][1] @= s.src.out + 1
s.reg = Wire(Bits32)
connect(s.wire[1][0], s.reg)
@update_ff
def up_reg():
s.reg <<= s.wire[0][0] + s.wire[0][1]
@update
def upA():
s.wire[1][1] @= s.reg + 1
@update
def up_to_sink():
s.sink.in_ @= s.wire[1][0] + s.wire[1][1]
def construct(s):
s.a = Wire(int)
s.b = Wire(int)
s.counter_assign = Wire(int)
s.counter_read = Wire(int)
@s.func
def assignb(b):
s.b = b + (s.counter_assign == -1) # never -1
@s.update
def up_write():
if s.counter_assign & 1:
assign(1, 2)
else:
assign(10, 20)
s.counter_assign += 1
@s.update
def up_read():
if s.counter_read & 1:
assert s.a == 1 and s.b == min(100, 2)
else:
assert s.a == 10 and s.b == 20
s.counter_read += 1
# The order doesn't matter. As a result, funcs should be processed
# after construction time
@s.func
def assign(a, b):
s.a = a + (s.counter_assign == -1)
assignb(b)
def construct(s):
s.src = TestSource([4, 3, 2, 1])
s.sink = TestSink([
"*", (4 + 1), (3 + 1) + (4 + 1), (2 + 1) + (3 + 1) + (4 + 1),
(1 + 1) + (2 + 1) + (3 + 1) + (4 + 1)
])
s.wire0 = Wire(int)
s.wire1 = Wire(int)
@s.update
def up_from_src():
s.wire0 = s.src.out + 1
s.reg0 = Wire(int)
# UPDATE ON EDGE!
@s.update_on_edge
def upA():
s.reg0 = s.wire0 + s.wire1
@s.update
def up_to_sink_and_loop_back():
s.sink.in_ = s.reg0
s.wire1 = s.reg0
def construct(s):
s.src = TestSource(int, [2, 1, 0, 2, 1, 0])
s.sink = TestSink(
int,
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[Wire(int) for _ in range(2)] for _ in range(2)]
connect(s.wire[0][0], s.src.out)
@s.update
def up_from_src():
s.wire[0][1] = s.src.out + 1
s.reg = Wire(int)
connect(s.wire[1][0], s.reg)
@s.update_on_edge
def up_reg():
s.reg = s.wire[0][0] + s.wire[0][1]
@s.update
def upA():
s.wire[1][1] = s.reg + 1
@s.update
def up_to_sink():
s.sink.in_ = s.wire[1][0] + s.wire[1][1]
def construct(s):
s.src = TestSource(int, [4, 3, 2, 1])
s.sink = TestSink(int, [
"*", (4 + 1), (3 + 1) + (4 + 1), (2 + 1) + (3 + 1) + (4 + 1),
(1 + 1) + (2 + 1) + (3 + 1) + (4 + 1)
])
s.wire0 = Wire(int)
s.wire1 = Wire(int)
@s.update
def up_from_src():
s.wire0 = s.src.out + 1
s.reg0 = Wire(int)
@s.update
def upA():
s.reg0 = s.wire0 + s.wire1
@s.update
def up_to_sink_and_loop_back():
s.sink.in_ = s.reg0
s.wire1 = s.reg0
s.add_constraints(
U(upA) < WR(s.wire1),
U(upA) < WR(s.wire0),
U(upA) < RD(s.reg0), # also implicit
)
def construct( s ):
s.a = Wire(Bits32)
s.b = Wire(Bits32)
s.counter_assign = Wire(Bits32)
s.counter_read = Wire(Bits32)
@s.func
def assignb( b ):
s.b @= b + zext(s.counter_assign < 0, 32) # never -1
@update
def up_write():
if s.counter_assign & 1:
assign( Bits32(1), Bits32(2) )
else:
assign( Bits32(10), Bits32(20) )
s.counter_assign @= s.counter_assign + 1
@update
def up_read():
if s.counter_read & 1:
assert s.a == 1 and s.b == min(100,2)
else:
assert s.a == 10 and s.b == 20
s.counter_read @= s.counter_read + 1
# The order doesn't matter. As a result, funcs should be processed
# after construction time
@s.func
def assign( a, b ):
s.a = a + zext( s.counter_assign < 0, 32)
assignb( b )
def construct(s):
s.src = TestSource(Bits32, [2, 1, 0, 2, 1, 0])
s.sink = TestSink(
Bits32,
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[Wire(32) for _ in range(2)] for _ in range(2)]
connect(s.wire[0][0], s.src.out)
@update
def up_from_src():
s.wire[0][1] @= s.src.out + 1
s.reg = Wire(32)
connect(s.wire[1][0], s.reg)
@update
def up_reg():
s.reg @= s.wire[0][0] + s.wire[0][1]
for i in range(2):
s.add_constraints(
U(up_reg) < WR(s.wire[0][i]), # up_reg reads s.wire[0][i]
)
@update
def upA():
s.wire[1][1] @= s.reg + 1
@update
def up_to_sink():
s.sink.in_ @= s.wire[1][0] + s.wire[1][1]
def construct(s):
s.src = TestSource(Bits32, [4, 3, 2, 1])
s.sink = TestSink(Bits32, [
"*", (4 + 1), (3 + 1) + (4 + 1), (2 + 1) + (3 + 1) + (4 + 1),
(1 + 1) + (2 + 1) + (3 + 1) + (4 + 1)
])
s.wire0 = Wire(Bits32)
s.wire1 = Wire(Bits32)
@s.update
def up_from_src():
s.wire0 = s.src.out + 1
s.reg0 = Wire(Bits32)
# UPDATE FF!
@s.update_ff
def upA():
s.reg0 <<= s.wire0 + s.wire1
@s.update
def up_to_sink_and_loop_back():
s.sink.in_ = s.reg0
s.wire1 = s.reg0
def construct( s ):
s.a = Wire()
s.b = Wire()
s.add_constraints(
WR(s.a) < RD(s.b),
)
def construct(s):
s.out = Wire(Bits32)
s.wire = Wire(Bits32)
connect(s.out, s.wire[0:32])
@update
def comb_upblk():
s.wire[0:16] @= 0
s.wire[16:32] @= 1
def construct(s):
s.x = Wire(SomeMsg)
s.A = Wire(SomeMsg)
connect(s.x, s.A)
@s.update
def up_wr_A_b():
s.A.b = Bits32(123)
def construct(s):
s.x = Wire(Bits24)
s.A = Wire(Bits32)
connect(s.x, s.A[8:32])
@update
def up_wr_As():
s.A[0:4] @= Bits4(0xf)
def construct(s):
s.x = Wire(Bits32)
s.A = Wire(Bits32)
connect(s.x, s.A)
@update
def up_wr_As():
s.A[0:24] @= Bits24(0x123456)
def construct(s):
s.x = Wire(Bits24)
s.A = Wire(Bits32)
connect(s.x, s.A[8:32])
@s.update
def up_wr_As():
s.A[0:24] = Bits24(0x123456)
def construct(s):
s.wire0 = Wire(Bits32)
s.wire1 = Wire(Bits32)
@s.update_ff
def up():
temp = s.wire1 + 1
s.wire0 <<= temp
s.wire1 <<= s.wire0 + 1
def construct( s ):
s.a = Wire(Bits1)
s.b = Wire(Bits1)
@update
def upA():
s.a @= s.b + 1
@update
def upB():
s.b @= s.b + 1
def construct(s):
s.a = Wire(SomeMsg)
s.b = Wire(int)
@s.update
def upA():
s.a.a.zzz = s.b + 1
@s.update
def upB():
s.b = s.b + 1
def construct(s):
s.a = Wire(int)
s.b = Wire(int)
@s.update
def upA():
s.a = s.b
@s.update
def upB():
s.b = s.a
def construct( s ):
s.a = Wire()
s.b = Wire()
@update
def upA():
s.a @= s.b
@update
def upB():
s.b @= s.a
def construct(s):
s.src = TestSource(int, [4, 3, 2, 1, 4, 3, 2, 1])
s.sink = TestSink(int, [
"*", (5 + 5 + 6 + 6), (4 + 4 + 5 + 5), (3 + 3 + 4 + 4),
(2 + 2 + 3 + 3), (5 + 5 + 6 + 6), (4 + 4 + 5 + 5),
(3 + 3 + 4 + 4), (2 + 2 + 3 + 3)
])
s.wire0 = Wire(int)
@s.update
def up_from_src():
s.wire0 = s.src.out + 1
s.reg = Wire(int)
@s.update_on_edge
def up_reg():
s.reg = s.wire0
s.wire1 = Wire(int)
s.wire2 = Wire(int)
connect(s.wire1, s.reg)
@s.update
def upA():
s.wire2 = s.reg + 1
s.wire3 = Wire(int)
s.wire4 = Wire(int)
connect(s.wire3, s.wire1)
connect(s.wire4, s.wire1)
s.wire5 = Wire(int)
s.wire6 = Wire(int)
connect(s.wire5, s.wire2)
connect(s.wire6, s.wire2)
s.wire7 = Wire(int)
s.wire8 = Wire(int)
@s.update
def upD():
s.wire7 = s.wire3 + s.wire6
s.wire8 = s.wire4 + s.wire5
@s.update
def up_to_sink():
s.sink.in_ = s.wire7 + s.wire8
def construct(s):
s.out = Wire(Bits32)
s.wire = Wire(Bits32)
connect(s.out, s.wire[0:32])
s.wire2 = Wire(Bits24)
connect(s.wire2[0:24], s.wire[8:32])
@update
def comb_upblk():
s.wire[0:16] @= 0
s.wire2[0:24] @= 1
def construct(s):
s.src = TestSource(Bits32, [4, 3, 2, 1, 4, 3, 2, 1])
s.sink = TestSink(Bits32, [
"*", (5 + 5 + 6 + 6), (4 + 4 + 5 + 5), (3 + 3 + 4 + 4),
(2 + 2 + 3 + 3), (5 + 5 + 6 + 6), (4 + 4 + 5 + 5),
(3 + 3 + 4 + 4), (2 + 2 + 3 + 3)
])
s.wire0 = Wire(Bits32)
@update
def up_from_src():
s.wire0 @= s.src.out + 1
s.reg = Wire(Bits32)
@update_ff
def up_reg():
s.reg <<= s.wire0
s.wire1 = Wire(Bits32)
s.wire2 = Wire(Bits32)
connect(s.wire1, s.reg)
@update
def upA():
s.wire2 @= s.reg + 1
s.wire3 = Wire(Bits32)
s.wire4 = Wire(Bits32)
connect(s.wire3, s.wire1)
connect(s.wire4, s.wire1)
s.wire5 = Wire(Bits32)
s.wire6 = Wire(Bits32)
connect(s.wire5, s.wire2)
connect(s.wire6, s.wire2)
s.wire7 = Wire(Bits32)
s.wire8 = Wire(Bits32)
@update
def upD():
s.wire7 @= s.wire3 + s.wire6
s.wire8 @= s.wire4 + s.wire5
@update
def up_to_sink():
s.sink.in_ @= s.wire7 + s.wire8
def construct(s):
s.wire0 = Wire(Bits32)
s.wire1 = Wire(Bits32)
@s.update_ff
def up_src():
s.wire0 <<= s.wire1 + 1
s.wire1 <<= s.wire0 + 1
@s.update
def comb():
s.wire1 = 1
def construct(s):
s.w = Wire(SomeMsg)
s.x = Wire(SomeMsg)
s.y = Wire(SomeMsg)
s.z = Wire(SomeMsg)
connect(s.w, s.x) # net1
connect(s.x.a, s.y.a) # net2
connect(s.y, s.z) # net3
@s.update
def up_wr_s_w():
s.w = SomeMsg(12, 123)
def construct(s):
s.x = Wire(Bits32)
s.A = Wire(SomeMsg)
connect(s.A.b, s.x)
@s.update
def up_wr_A():
s.A = SomeMsg(12, 123)
@s.update
def up_rd_x():
z = s.x
def construct(s):
s.x = Wire(Bits24)
s.A = Wire(Bits32)
connect(s.x, s.A[8:32])
@update
def up_wr_As():
s.A[0:24] @= Bits24(0x123456)
@update
def up_wr_x():
s.x @= Bits24(0x654321)
def construct(s):
s.x = Wire(SomeMsg)
s.A = Wire(SomeMsg)
connect(s.x, s.A)
@s.update
def up_wr_x():
s.x = SomeMsg(12, 123)
@s.update
def up_rd_A_b():
assert s.A.b == 123
def construct(s):
s.x = Wire(Bits24)
s.A = Wire(Bits32)
connect(s.A[8:32], s.x)
@update
def up_wr_A():
s.A @= Bits32(0x12345678)
@update
def up_rd_x():
assert s.x == 0x123456
def construct(s):
s.w = Wire(Bits32)
s.x = Wire(Bits32)
s.y = Wire(Bits32)
s.z = Wire(Bits32)
connect(s.w[0:16], s.x[8:24]) # net1
connect(s.x[16:32], s.y[0:16]) # net2
connect(s.y[8:24], s.z[0:16]) # net3
@update
def up_wr_s_w():
s.w @= Bits32(0x12345678)