def construct(s):
s.src = TestSource(int, [4, 3, 2, 1])
s.sink = TestSink(int, [
"*", (4 + 1), (3 + 1) + (4 + 1), (2 + 1) + (3 + 1) + (4 + 1),
(1 + 1) + (2 + 1) + (3 + 1) + (4 + 1)
])
s.wire0 = Wire(int)
s.wire1 = Wire(int)
@s.update
def up_from_src():
s.wire0 = s.src.out + 1
s.reg0 = Wire(int)
@s.update
def upA():
s.reg0 = s.wire0 + s.wire1
@s.update
def up_to_sink_and_loop_back():
s.sink.in_ = s.reg0
s.wire1 = s.reg0
s.add_constraints(
U(upA) < WR(s.wire1),
U(upA) < WR(s.wire0),
U(upA) < RD(s.reg0), # also implicit
)
def construct(s):
@s.update
def upA():
pass
@s.update
def upB():
pass
s.add_constraints(
U(upA) < U(upB),
U(upB) < U(upA),
)
def construct(s):
s.src = TestSource([5, 4, 3, 2, 1])
s.sink = TestSink([0, 5, 4, 3, 2])
s.wire0 = 0
s.wire1 = 0
@s.update
def up_from_src():
s.wire0 = s.src.out
up_src = s.src.get_update_block("up_src")
s.add_constraints(U(up_src) < U(up_from_src), )
@s.update
def up_reg():
s.wire1 = s.wire0
@s.update
def up_to_sink():
s.sink.in_ = s.wire1
s.add_constraints(
U(up_reg) < U(up_to_sink),
U(up_reg) < U(up_from_src),
)
up_sink = s.sink.get_update_block("up_sink")
s.add_constraints(U(up_to_sink) < U(up_sink), )
def construct(s):
s.src = TestSource(Bits32, [2, 1, 0, 2, 1, 0])
s.sink = TestSink(
Bits32,
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[Wire(32) for _ in range(2)] for _ in range(2)]
connect(s.wire[0][0], s.src.out)
@update
def up_from_src():
s.wire[0][1] @= s.src.out + 1
s.reg = Wire(32)
connect(s.wire[1][0], s.reg)
@update
def up_reg():
s.reg @= s.wire[0][0] + s.wire[0][1]
for i in range(2):
s.add_constraints(
U(up_reg) < WR(s.wire[0][i]), # up_reg reads s.wire[0][i]
)
@update
def upA():
s.wire[1][1] @= s.reg + 1
@update
def up_to_sink():
s.sink.in_ @= s.wire[1][0] + s.wire[1][1]
def construct(s):
s.src = TestSource(int, [4, 3, 2, 1, 4, 3, 2, 1])
s.sink = TestSink(int, [5, 4, 3, 2, 5, 4, 3, 2])
@s.update
def up_from_src():
s.sink.in_ = s.src.out + 1
s.add_constraints(U(up_from_src) < RD(s.sink.in_), )
def construct(s):
s.src = TestSource([2, 1, 0, 2, 1, 0])
s.sink = TestSink(
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[0 for _ in range(2)] for _ in range(2)]
@s.update
def up_from_src():
s.wire[0][0] = s.src.out
s.wire[0][1] = s.src.out + 1
up_src = s.src.get_update_block("up_src")
s.add_constraints(U(up_src) < U(up_from_src), )
s.reg = 0
@s.update
def up_reg():
s.reg = s.wire[0][0] + s.wire[0][1]
@s.update
def upA():
s.wire[1][0] = s.reg
s.wire[1][1] = s.reg + 1
s.add_constraints(
U(up_reg) < U(upA),
U(up_reg) < U(up_from_src),
)
@s.update
def up_to_sink():
s.sink.in_ = s.wire[1][0] + s.wire[1][1]
up_sink = s.sink.get_update_block("up_sink")
s.add_constraints(
U(upA) < U(up_to_sink),
U(up_to_sink) < U(up_sink),
)
def construct(s, msgs):
s.msgs = list(msgs)
s.queue = deque(maxlen=1)
s.idx = 0
s.resp = CalleePort(method=s.resp_)
s.resp_rdy = CalleePort(method=s.resp_rdy_)
s.v = None
@update_once
def up_sink():
s.v = None
if s.queue:
msg = s.queue.popleft()
s.v = msg
if s.idx >= len(s.msgs):
raise TestSinkError("""
The test sink received a message that !
- sink name : {}
- msg number : {}
- actual msg : {}
""".format(s, s.idx, msg))
else:
ref = s.msgs[s.idx]
s.idx += 1
if msg != ref:
raise TestSinkError("""
The test sink received an incorrect message!
- sink name : {}
- msg number : {}
- expected msg : {}
- actual msg : {}
""".format(s, s.idx, ref, msg))
s.add_constraints(
U(up_sink) < M(s.resp_), # pipe behavior
U(up_sink) < M(s.resp_rdy_),
)
def construct(s):
s.src = TestSource([4, 3, 2, 1])
s.sink = TestSink([
"*", (4 + 1), (3 + 1) + (4 + 1), (2 + 1) + (3 + 1) + (4 + 1),
(1 + 1) + (2 + 1) + (3 + 1) + (4 + 1)
])
s.wire0 = 0
s.wire1 = 0
@s.update
def up_from_src():
s.wire0 = s.src.out + 1
up_src = s.src.get_update_block("up_src")
s.add_constraints(U(up_src) < U(up_from_src), )
s.reg0 = 0
@s.update
def upA():
s.reg0 = s.wire0 + s.wire1
@s.update
def up_to_sink_and_loop_back():
s.sink.in_ = s.reg0
s.wire1 = s.reg0
s.add_constraints(
U(upA) < U(up_to_sink_and_loop_back),
U(upA) < U(up_from_src),
)
up_sink = s.sink.get_update_block("up_sink")
s.add_constraints(U(up_to_sink_and_loop_back) < U(up_sink), )
def construct(s):
s.src = TestSource(int, [2, 1, 0, 2, 1, 0])
s.sink = TestSink(
int,
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[Wire(int) for _ in range(2)] for _ in range(2)]
@s.update
def up_from_src():
s.wire[0][0] = s.src.out
s.wire[0][1] = s.src.out + 1
s.reg = Wire(int)
@s.update
def up_reg():
s.reg = s.wire[0][0] + s.wire[0][1]
s.add_constraints(
U(up_reg) < RD(s.reg), # up_reg writes s.reg
)
@s.update
def upA():
for i in range(2):
s.wire[1][i] = s.reg + i
for i in range(2):
s.add_constraints(
U(up_reg) < WR(s.wire[0][i]), # up_reg reads s.wire[0][i]
)
@s.update
def up_to_sink():
s.sink.in_ = s.wire[1][0] + s.wire[1][1]
up_sink = s.sink.get_update_block("up_sink")
s.add_constraints(
U(upA) < U(up_to_sink),
U(up_to_sink) < U(up_sink),
)
def construct(s):
s.src = TestSource([4, 3, 2, 1, 4, 3, 2, 1])
s.sink = TestSink([
"*", (5 + 6 + 6 + 7), (4 + 5 + 5 + 6), (3 + 4 + 4 + 5),
(2 + 3 + 3 + 4), (5 + 6 + 6 + 7), (4 + 5 + 5 + 6),
(3 + 4 + 4 + 5), (2 + 3 + 3 + 4)
])
s.wire0 = 0
@s.update
def up_from_src():
s.wire0 = s.src.out + 1
up_src = s.src.get_update_block("up_src")
s.add_constraints(U(up_src) < U(up_from_src), )
s.reg = 0
@s.update
def up_reg():
s.reg = s.wire0
s.wire1 = s.wire2 = 0
@s.update
def upA():
s.wire1 = s.reg
s.wire2 = s.reg + 1
s.add_constraints(
U(up_reg) < U(upA),
U(up_reg) < U(up_from_src),
)
s.wire3 = s.wire4 = 0
@s.update
def upB():
s.wire3 = s.wire1
s.wire4 = s.wire1 + 1
s.wire5 = s.wire6 = 0
@s.update
def upC():
s.wire5 = s.wire2
s.wire6 = s.wire2 + 1
s.add_constraints(
U(upA) < U(upB),
U(upA) < U(upC),
)
s.wire7 = s.wire8 = 0
@s.update
def upD():
s.wire7 = s.wire3 + s.wire6
s.wire8 = s.wire4 + s.wire5
s.add_constraints(
U(upB) < U(upD),
U(upC) < U(upD),
)
@s.update
def up_to_sink():
s.sink.in_ = s.wire7 + s.wire8
up_sink = s.sink.get_update_block("up_sink")
s.add_constraints(
U(upD) < U(up_to_sink),
U(up_to_sink) < U(up_sink),
)