def construct(s):
s.src = TestSource(int, [4, 3, 2, 1])
s.sink = TestSink(int, [
"*", (4 + 1), (3 + 1) + (4 + 1), (2 + 1) + (3 + 1) + (4 + 1),
(1 + 1) + (2 + 1) + (3 + 1) + (4 + 1)
])
s.wire0 = Wire(int)
s.wire1 = Wire(int)
@s.update
def up_from_src():
s.wire0 = s.src.out + 1
s.reg0 = Wire(int)
@s.update
def upA():
s.reg0 = s.wire0 + s.wire1
@s.update
def up_to_sink_and_loop_back():
s.sink.in_ = s.reg0
s.wire1 = s.reg0
s.add_constraints(
U(upA) < WR(s.wire1),
U(upA) < WR(s.wire0),
U(upA) < RD(s.reg0), # also implicit
)
def construct(s):
s.src = TestSource(Bits32, [2, 1, 0, 2, 1, 0])
s.sink = TestSink(
Bits32,
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[Wire(32) for _ in range(2)] for _ in range(2)]
connect(s.wire[0][0], s.src.out)
@update
def up_from_src():
s.wire[0][1] @= s.src.out + 1
s.reg = Wire(32)
connect(s.wire[1][0], s.reg)
@update
def up_reg():
s.reg @= s.wire[0][0] + s.wire[0][1]
for i in range(2):
s.add_constraints(
U(up_reg) < WR(s.wire[0][i]), # up_reg reads s.wire[0][i]
)
@update
def upA():
s.wire[1][1] @= s.reg + 1
@update
def up_to_sink():
s.sink.in_ @= s.wire[1][0] + s.wire[1][1]
def construct( s ):
s.a = Wire()
s.b = Wire()
s.add_constraints(
WR(s.a) < RD(s.b),
)
def construct(s):
s.src = TestSource(int, [2, 1, 0, 2, 1, 0])
s.sink = TestSink(
int,
["*", (5 + 6), (3 + 4), (1 + 2), (5 + 6), (3 + 4), (1 + 2)])
s.wire = [[Wire(int) for _ in range(2)] for _ in range(2)]
@s.update
def up_from_src():
s.wire[0][0] = s.src.out
s.wire[0][1] = s.src.out + 1
s.reg = Wire(int)
@s.update
def up_reg():
s.reg = s.wire[0][0] + s.wire[0][1]
s.add_constraints(
U(up_reg) < RD(s.reg), # up_reg writes s.reg
)
@s.update
def upA():
for i in range(2):
s.wire[1][i] = s.reg + i
for i in range(2):
s.add_constraints(
U(up_reg) < WR(s.wire[0][i]), # up_reg reads s.wire[0][i]
)
@s.update
def up_to_sink():
s.sink.in_ = s.wire[1][0] + s.wire[1][1]
up_sink = s.sink.get_update_block("up_sink")
s.add_constraints(
U(upA) < U(up_to_sink),
U(up_to_sink) < U(up_sink),
)