def construct(s, DataType, CtrlType, Fu0, Fu1, num_inports, num_outports,
data_mem_size):
# Constant
AddrType = mk_bits(clog2(data_mem_size))
s.const_zero = DataType(0, 0)
# Interface
s.recv_in = [RecvIfcRTL(DataType) for _ in range(num_inports)]
s.recv_const = RecvIfcRTL(DataType)
s.recv_opt = RecvIfcRTL(CtrlType)
s.send_out = [SendIfcRTL(DataType) for _ in range(num_outports)]
# Redundant interfaces for MemUnit
s.to_mem_raddr = SendIfcRTL(AddrType)
s.from_mem_rdata = RecvIfcRTL(DataType)
s.to_mem_waddr = SendIfcRTL(AddrType)
s.to_mem_wdata = SendIfcRTL(DataType)
# Components
s.Fu0 = Fu0(DataType, CtrlType, 2, 1, data_mem_size)
s.Fu1 = Fu1(DataType, CtrlType, 2, 1, data_mem_size)
# Connections
s.recv_in[0].msg //= s.Fu0.recv_in[0].msg
s.recv_in[1].msg //= s.Fu0.recv_in[1].msg
s.recv_in[2].msg //= s.Fu1.recv_in[1].msg
# s.Fu0.recv_opt.msg //= s.recv_opt.msg
# s.Fu1.recv_opt.msg //= s.recv_opt.msg
s.Fu0.send_out[0].msg //= s.Fu1.recv_in[0].msg
s.Fu1.send_out[0].msg //= s.send_out[0].msg
s.Fu0.recv_const //= s.recv_const
@s.update
def update_signal():
s.recv_in[0].rdy = s.send_out[0].rdy
s.recv_in[1].rdy = s.send_out[0].rdy
s.recv_in[2].rdy = s.send_out[0].rdy
s.Fu0.recv_opt.en = s.recv_opt.en
s.Fu1.recv_opt.en = s.recv_opt.en
s.recv_opt.rdy = s.send_out[0].rdy
# s.send_out[0].en = s.recv_in[0].en and s.recv_in[1].en and\
# s.recv_in[2].en and s.recv_opt.en
s.send_out[0].en = s.recv_in[0].en and s.recv_opt.en
@s.update
def update_mem():
s.to_mem_waddr.en = b1(0)
s.to_mem_wdata.en = b1(0)
s.to_mem_wdata.msg = s.const_zero
s.to_mem_waddr.msg = AddrType(0)
s.to_mem_raddr.msg = AddrType(0)
s.to_mem_raddr.en = b1(0)
s.from_mem_rdata.rdy = b1(0)
def construct(s, DataType, latency=1):
# Constant
s.latency = latency
s.num_entries = 2
s.data = DataType(0)
# Interface
s.recv = RecvIfcRTL(DataType)
s.send = SendIfcRTL(DataType)
# Component
s.queues = [
NormalQueueRTL(DataType, s.num_entries) for _ in range(s.latency)
]
@s.update
def process():
s.recv.rdy = s.queues[0].enq.rdy
s.queues[0].enq.msg = s.recv.msg
s.queues[0].enq.en = s.recv.en and s.queues[0].enq.rdy
for i in range(s.latency - 1):
s.queues[i + 1].enq.msg = s.queues[i].deq.ret
s.queues[
i +
1].enq.en = s.queues[i].deq.rdy and s.queues[i + 1].enq.rdy
s.queues[i].deq.en = s.queues[i + 1].enq.en
s.send.msg = s.queues[s.latency - 1].deq.ret
s.send.en = s.send.rdy and s.queues[s.latency - 1].deq.rdy
s.queues[s.latency - 1].deq.en = s.send.en
def construct( s, DataType, nregs ):
# Constant
AddrType = mk_bits( clog2( nregs ) )
# Interface
s.recv_waddr = RecvIfcRTL( AddrType )
s.recv_wdata = RecvIfcRTL( DataType )
s.recv_raddr = RecvIfcRTL( AddrType )
s.send_rdata = SendIfcRTL( DataType )
# Component
s.reg_file = RegisterFile( DataType, nregs )
# Connections
s.reg_file.raddr[0] //= s.recv_raddr.msg
s.reg_file.waddr[0] //= s.recv_waddr.msg
s.reg_file.wdata[0] //= s.recv_wdata.msg
s.send_rdata.msg //= s.reg_file.rdata[0]
s.reg_file.wen[0] //= b1( 1 )
@s.update
def update_signal():
s.recv_raddr.rdy = s.send_rdata.rdy
s.recv_waddr.rdy = s.send_rdata.rdy
s.recv_wdata.rdy = s.send_rdata.rdy
s.send_rdata.en = s.recv_raddr.en
def construct(s, DataType, const_list=None):
# Constant
num_const = len(const_list)
AddrType = mk_bits(clog2(num_const + 1))
TimeType = mk_bits(clog2(num_const + 1))
# Interface
s.send_const = SendIfcRTL(DataType)
# Component
s.const_queue = [DataType(0) for _ in range(num_const)]
for i in range(len(const_list)):
s.const_queue[i] = const_list[i]
s.cur = Wire(AddrType)
@s.update
def load():
s.send_const.msg = s.const_queue[s.cur]
@s.update
def update_en():
s.send_const.en = s.send_const.rdy
@s.update_ff
def update_raddr():
if s.send_const.rdy:
if s.cur + AddrType(1) >= AddrType(num_const):
s.cur <<= AddrType(0)
else:
s.cur <<= s.cur + AddrType(1)
def construct( s, Type ):
s.in_ = InValRdyIfc( Type )
s.send = SendIfcRTL ( Type )
s.in_.rdy //= s.send.rdy
s.send.en //= lambda: s.send.rdy & s.in_.val
s.send.msg //= s.in_.msg
def construct(
s,
PacketType,
PositionType,
k_ary,
n_fly,
InputUnitType=InputUnitRTL,
RouteUnitType=DTRBflyRouteUnitRTL,
SwitchUnitType=SwitchUnitRTL,
OutputUnitType=OutputUnitRTL,
):
s.dim = PhysicalDimension()
s.num_inports = k_ary
s.num_outports = k_ary
# Interface
s.pos = InPort(PositionType)
s.recv = [RecvIfcRTL(PacketType) for _ in range(s.num_inports)]
s.send = [SendIfcRTL(PacketType) for _ in range(s.num_outports)]
# Components
s.input_units = [
InputUnitType(PacketType) for _ in range(s.num_inports)
]
s.route_units = [
RouteUnitType(PacketType,
PositionType,
s.num_outports,
n_fly=n_fly) for i in range(s.num_inports)
]
s.switch_units = [
SwitchUnitType(PacketType, s.num_inports)
for _ in range(s.num_outports)
]
s.output_units = [
OutputUnitType(PacketType) for _ in range(s.num_outports)
]
# Connection
for i in range(s.num_inports):
s.recv[i] //= s.input_units[i].recv
s.input_units[i].give //= s.route_units[i].get
s.pos //= s.route_units[i].pos
for i in range(s.num_inports):
for j in range(s.num_outports):
s.route_units[i].give[j] //= s.switch_units[j].get[i]
for j in range(s.num_outports):
s.switch_units[j].give //= s.output_units[j].get
s.output_units[j].send //= s.send[j]
def construct(
s,
Header,
num_inports=2,
num_outports=2,
InputUnitType=InputUnitRTL,
RouteUnitType=XbarRouteUnitMflitRTL,
SwitchUnitType=SwitchUnitGrantHoldRTL,
OutputUnitType=OutputUnitRTL,
):
# Local parameter
s.num_inports = num_inports
s.num_outports = num_outports
s.PhitType = mk_bits(Header.nbits)
# Special case for num_inports = 1
if num_inports == 1: SwitchUnitType = SwitchUnitNullRTL
# Interface
s.recv = [RecvIfcRTL(s.PhitType) for _ in range(s.num_inports)]
s.send = [SendIfcRTL(s.PhitType) for _ in range(s.num_outports)]
# Components
s.input_units = [
InputUnitType(s.PhitType) for _ in range(s.num_inports)
]
s.route_units = [
RouteUnitType(Header, s.num_outports) for i in range(s.num_inports)
]
s.switch_units = [
SwitchUnitType(s.PhitType, s.num_inports)
for _ in range(s.num_outports)
]
s.output_units = [
OutputUnitType(s.PhitType) for _ in range(s.num_outports)
]
# Connections
for i in range(s.num_inports):
s.recv[i] //= s.input_units[i].recv
s.input_units[i].give //= s.route_units[i].get
for i in range(s.num_inports):
for j in range(s.num_outports):
s.route_units[i].give[j] //= s.switch_units[j].get[i]
s.route_units[i].hold[j] //= s.switch_units[j].hold[i]
for j in range(s.num_outports):
s.switch_units[j].give //= s.output_units[j].get
s.output_units[j].send //= s.send[j]
def construct(
s,
PositionType,
InputUnitType=InputUnitRTL,
RouteUnitType=PitonRouteUnit,
SwitchUnitType=SwitchUnitGrantHoldRTL,
OutputUnitType=OutputUnitRTL,
):
# Local parameter
s.num_inports = 5
s.num_outports = 5
assert PitonNoCHeader.nbits == 64
s.PhitType = Bits64
# Interface
s.recv = [RecvIfcRTL(s.PhitType) for _ in range(s.num_inports)]
s.send = [SendIfcRTL(s.PhitType) for _ in range(s.num_outports)]
s.pos = InPort(PositionType)
# Components
s.input_units = [
InputUnitType(s.PhitType, QueueType=NormalQueueRTL)
for _ in range(s.num_inports)
]
s.route_units = [
RouteUnitType(PositionType) for i in range(s.num_inports)
]
s.switch_units = [
SwitchUnitType(s.PhitType, s.num_inports)
for _ in range(s.num_outports)
]
s.output_units = [
OutputUnitType(s.PhitType) for _ in range(s.num_outports)
]
# Connections
for i in range(s.num_inports):
s.recv[i] //= s.input_units[i].recv
s.input_units[i].give //= s.route_units[i].get
s.pos //= s.route_units[i].pos
for i in range(s.num_inports):
for j in range(s.num_outports):
s.route_units[i].give[j] //= s.switch_units[j].get[i]
s.route_units[i].hold[j] //= s.switch_units[j].hold[i]
for j in range(s.num_outports):
s.switch_units[j].give //= s.output_units[j].get
s.output_units[j].send //= s.send[j]
def construct(s,
DataType,
PredicateType,
CtrlType,
num_inports,
num_outports,
data_mem_size=4):
# Constant
AddrType = mk_bits(clog2(data_mem_size))
s.const_zero = DataType(0, 0)
num_entries = 2
CountType = mk_bits(clog2(num_entries + 1))
FuInType = mk_bits(clog2(num_inports + 1))
# Interface
s.recv_in = [RecvIfcRTL(DataType) for _ in range(num_inports)]
s.recv_in_count = [InPort(CountType) for _ in range(num_inports)]
s.recv_predicate = RecvIfcRTL(PredicateType)
s.recv_const = RecvIfcRTL(DataType)
s.recv_opt = RecvIfcRTL(CtrlType)
s.send_out = [SendIfcRTL(DataType) for _ in range(num_outports)]
# Redundant interfaces for MemUnit
s.to_mem_raddr = SendIfcRTL(AddrType)
s.from_mem_rdata = RecvIfcRTL(DataType)
s.to_mem_waddr = SendIfcRTL(AddrType)
s.to_mem_wdata = SendIfcRTL(DataType)
@s.update
def update_signal():
for j in range(num_outports):
s.recv_const.rdy = s.send_out[j].rdy or s.recv_const.rdy
s.recv_opt.rdy = s.send_out[j].rdy or s.recv_opt.rdy
@s.update
def update_mem():
s.to_mem_waddr.en = b1(0)
s.to_mem_wdata.en = b1(0)
s.to_mem_wdata.msg = s.const_zero
s.to_mem_waddr.msg = AddrType(0)
s.to_mem_raddr.msg = AddrType(0)
s.to_mem_raddr.en = b1(0)
s.from_mem_rdata.rdy = b1(0)
def construct(
s,
Header,
PositionType,
InputUnitType=InputUnitRTL,
RouteUnitType=MeshRouteUnitRTLMflitXY,
SwitchUnitType=SwitchUnitGrantHoldRTL,
OutputUnitType=OutputUnitRTL,
):
# Local parameter
s.num_inports = 5
s.num_outports = 5
s.PhitType = mk_bits(Header.nbits)
# Interface
s.recv = [RecvIfcRTL(s.PhitType) for _ in range(s.num_inports)]
s.send = [SendIfcRTL(s.PhitType) for _ in range(s.num_outports)]
s.pos = InPort(PositionType)
# Components
s.input_units = [
InputUnitType(s.PhitType) for _ in range(s.num_inports)
]
s.route_units = [
RouteUnitType(Header, PositionType) for i in range(s.num_inports)
]
s.switch_units = [
SwitchUnitType(s.PhitType, s.num_inports)
for _ in range(s.num_outports)
]
s.output_units = [
OutputUnitType(s.PhitType) for _ in range(s.num_outports)
]
# Connections
for i in range(s.num_inports):
s.recv[i] //= s.input_units[i].recv
s.input_units[i].give //= s.route_units[i].get
s.pos //= s.route_units[i].pos
for i in range(s.num_inports):
for j in range(s.num_outports):
s.route_units[i].give[j] //= s.switch_units[j].get[i]
s.route_units[i].hold[j] //= s.switch_units[j].hold[i]
for j in range(s.num_outports):
s.switch_units[j].give //= s.output_units[j].get
s.output_units[j].send //= s.send[j]
def construct( s, DataType, CtrlType,
num_inports=5, num_outports=5, bypass_point=4 ):
OutType = mk_bits( clog2( num_inports + 1 ) )
s.bypass_point = bypass_point
# Interface
s.recv_opt = RecvIfcRTL( CtrlType )
s.recv_data = [ RecvIfcRTL( DataType ) for _ in range ( num_inports ) ]
s.send_data = [ SendIfcRTL( DataType ) for _ in range ( num_outports ) ]
# TODO: should include position information or not?
# s.pos = InPort( PositionType )
# Routing logic
@s.update
def update_signal():
out_rdy = b1( 0 )
if s.recv_opt.msg.ctrl != OPT_START:
for i in range( num_outports ):
in_dir = s.recv_opt.msg.outport[i]
out_rdy = out_rdy | s.send_data[i].rdy
# s.send_data[i].msg.bypass = b1( 0 )
if in_dir > OutType( 0 ) and s.send_data[i].rdy:
in_dir = in_dir - OutType( 1 )
s.recv_data[in_dir].rdy = s.send_data[i].rdy
s.send_data[i].en = s.recv_data[in_dir].en
if s.send_data[i].en and s.recv_data[in_dir].rdy:
s.send_data[i].msg.payload = s.recv_data[in_dir].msg.payload
s.send_data[i].msg.predicate = s.recv_data[in_dir].msg.predicate
# s.send_data[i].msg = s.recv_data[in_dir].msg
s.send_data[i].msg.bypass = s.recv_data[in_dir].msg.bypass
# The generate one can be send to other tile without buffering,
# but buffering is still needed when 'other tile' is yourself
# (i.e., generating output to self input). Here we avoid self
# connecting by checking whether the inport belongs to FU and
# outport be towards to remote tiles to eliminate combinational
# loop.
if in_dir >= OutType( s.bypass_point ) and i<s.bypass_point:
s.send_data[i].msg.bypass = b1( 1 )
# print("in crossbar ", s, " set bypass ... s.recv_opt.msg.outport[", i, "]: ", s.recv_opt.msg.outport[i])
else:
s.send_data[i].msg.bypass = b1( 0 )
# print("in crossbar if... s.send_data[", i, "].msg: ", s.send_data[i].msg, "; recv.rdy: ", s.recv_data[in_dir].rdy)
else:
s.send_data[i].en = b1( 0 )
#s.send_data[i].msg = b1( 0 )
# print("in crossbar else... s.send_data[", i, "].msg: ", s.send_data[i].msg)
else:
for i in range( num_outports ):
# s.send_data[i].msg.bypass = b1( 0 )
s.send_data[i].en = b1( 0 )
s.recv_opt.rdy = out_rdy
def construct(s, MsgType, vc=2, credit_line=1, QType=BypassQueueRTL):
assert vc > 1
# Interface
s.recv = CreditRecvIfcRTL(MsgType, vc)
s.send = SendIfcRTL(MsgType)
s.MsgType = MsgType
s.vc = vc
# Components
CreditType = mk_bits(clog2(credit_line + 1))
s.buffers = [
QType(MsgType, num_entries=credit_line) for _ in range(vc)
]
s.arbiter = RoundRobinArbiterEn(nreqs=vc)
s.encoder = Encoder(in_nbits=vc, out_nbits=clog2(vc))
for i in range(vc):
s.buffers[i].enq.msg //= s.recv.msg
s.buffers[i].deq.rdy //= s.arbiter.reqs[i]
s.arbiter.grants //= s.encoder.in_
s.arbiter.en //= s.send.en
@update
def up_enq():
if s.recv.en:
for i in range(vc):
s.buffers[i].enq.en @= s.recv.msg.vc_id == i
else:
for i in range(vc):
s.buffers[i].enq.en @= 0
@update
def up_deq_and_send():
for i in range(vc):
s.buffers[i].deq.en @= 0
s.send.msg @= s.buffers[s.encoder.out].deq.ret
if s.send.rdy & (s.arbiter.grants > 0):
s.send.en @= 1
s.buffers[s.encoder.out].deq.en @= 1
else:
s.send.en @= 0
@update
def up_yummy():
for i in range(vc):
s.recv.yum[i] @= s.buffers[i].deq.en
def construct(s, Type, msgs, initial_delay=0, interval_delay=0):
# Interface
s.send = SendIfcRTL(Type)
# Components
s.src = TestSrcCL(Type, msgs, initial_delay, interval_delay)
s.adapter = RecvCL2SendRTL(Type)
connect(s.src.send, s.adapter.recv)
connect(s.adapter.send, s.send)
def construct(s, proc, imem, dmem, xcel):
CacheReqType, CacheRespType = mk_mem_msg(8, 32, 32)
MemReqType, MemRespType = mk_mem_msg(8, 32, 128)
# interface to outside ProcMemXcel
s.go = InPort()
s.stats_en = OutPort()
s.mngr2proc = RecvIfcRTL(Bits32)
s.proc2mngr = SendIfcRTL(Bits32)
s.imem = MemMasterIfcRTL(MemReqType, MemRespType)
s.dmem = MemMasterIfcRTL(MemReqType, MemRespType)
s.proc = proc
s.xcel = xcel
s.icache = imem
s.dcache = dmem
s.funnel = Funnel(CacheReqType, 2)(
in_={
0: s.proc.dmem.req,
1: s.xcel.mem.req
},
out=s.dcache.cache.req,
)
s.router = Router(CacheRespType, 2)(in_=s.dcache.cache.resp,
out={
0: s.proc.dmem.resp,
1: s.xcel.mem.resp
})
# connect signals
s.stats_en //= s.proc.stats_en
s.proc2mngr //= s.proc.proc2mngr
s.mngr2proc //= s.proc.mngr2proc
# proc
s.proc.core_id //= 0
s.xcel.xcel //= s.proc.xcel
s.icache.cache //= s.proc.imem
# mem
s.imem //= s.icache.mem
s.dmem //= s.dcache.mem
def construct(s, MsgType, nports):
DataType = mk_bits(nports)
OpaqueType = MsgType.get_field_type('opaque')
#---------------------------------------------------------------------
# Interface
#---------------------------------------------------------------------
s.in_ = [RecvIfcRTL(MsgType) for _ in range(nports)]
s.out = SendIfcRTL(MsgType)
s.qs = [
BypassQueueRTL(MsgType, 1)(enq=s.in_[i]) for i in range(nports)
]
#---------------------------------------------------------------------
# Setup round robin arbiter
#---------------------------------------------------------------------
# Notice that we AND the output ready with each request signal, so
# if the output port is not ready we do not make any requests to the
# arbiter. This will prevent the arbiter priority from changing.
s.vals = Wire(mk_bits(nports))
s.arbiter = RoundRobinArbiterEn(nports)(en=1)
@s.update
def arbiter_logic():
s.vals = DataType(0)
s.arbiter.reqs = DataType(0)
for i in range(nports):
s.qs[i].deq.en = b1(0)
for i in range(nports):
s.vals[i] = s.qs[i].deq.rdy
s.arbiter.reqs[i] = s.qs[i].deq.rdy & s.out.rdy
s.qs[i].deq.en = s.arbiter.grants[i]
#---------------------------------------------------------------------
# Assign outputs
#---------------------------------------------------------------------
@s.update
def output_logic():
s.out.en = reduce_or(s.vals) & s.out.rdy
s.out.msg = MsgType()
for i in range(nports):
if s.arbiter.grants[i]:
s.out.msg = deepcopy(s.qs[i].deq.ret)
s.out.msg.opaque = OpaqueType(i)
def construct(
s,
PacketType,
PositionType,
num_routers=4,
chl_lat=0,
vc=2,
credit_line=2,
):
# Constants
s.num_routers = num_routers
# IDType = mk_bits(clogs(num_routers))
# Interface
s.recv = [RecvIfcRTL(PacketType) for _ in range(s.num_routers)]
s.send = [SendIfcRTL(PacketType) for _ in range(s.num_routers)]
# Components
s.routers = [
RingRouterRTL(PacketType, PositionType, num_routers, vc=vc)
for i in range(num_routers)
]
s.recv_adp = [
RecvRTL2CreditSendRTL(PacketType, vc=vc, credit_line=credit_line)
for _ in range(num_routers)
]
s.send_adp = [
CreditRecvRTL2SendRTL(PacketType, vc=vc, credit_line=credit_line)
for _ in range(num_routers)
]
# Connect s.routers together in ring
for i in range(s.num_routers):
next_id = (i + 1) % num_routers
s.routers[i].send[RIGHT] //= s.routers[next_id].recv[LEFT]
s.routers[next_id].send[LEFT] //= s.routers[i].recv[RIGHT]
# Connect the self port (with Network Interface)
s.recv[i] //= s.recv_adp[i].recv
s.recv_adp[i].send //= s.routers[i].recv[SELF]
s.routers[i].send[SELF] //= s.send_adp[i].recv
s.send_adp[i].send //= s.send[i]
@update
def up_pos():
for r in range(s.num_routers):
s.routers[r].pos @= r
def construct(s, PacketType, QueueType=NormalQueueRTL, latency=0):
# Constant
s.dim = PhysicalDimension()
s.QueueType = QueueType
s.latency = latency
s.num_entries = 2
# Interface
s.recv = RecvIfcRTL(PacketType)
s.send = SendIfcRTL(PacketType)
if s.QueueType != None and s.latency > 0:
# Component
s.queues = [
s.QueueType(PacketType, s.num_entries)
for _ in range(s.latency)
]
# Connections
s.recv.rdy //= s.queues[0].enq.rdy
s.queues[0].enq.msg //= s.recv.msg
for i in range(s.latency - 1):
s.queues[i + 1].enq.msg //= s.queues[i].deq.ret
s.queues[-1].deq.ret //= s.send.msg
@update
def process():
s.queues[0].enq.en @= s.recv.en & s.queues[0].enq.rdy
for i in range(s.latency - 1):
s.queues[i + 1].enq.en @= s.queues[i].deq.rdy & s.queues[
i + 1].enq.rdy
s.queues[i].deq.en @= s.queues[i].deq.rdy & s.queues[
i + 1].enq.rdy
s.send.en @= s.send.rdy & s.queues[s.latency - 1].deq.rdy
s.queues[s.latency -
1].deq.en @= s.send.rdy & s.queues[s.latency -
1].deq.rdy
else:
# If latency==0 simply bypass
s.recv //= s.send
def construct(s, Type):
s.drop = InPort(Bits1)
s.in_ = RecvIfcRTL(Type)
s.out = SendIfcRTL(Type)
s.in_.msg //= s.out.msg
s.snoop_state = RegRst(Bits1, reset_value=0)
@s.update
def state_transitions():
curr_state = s.snoop_state.out
s.snoop_state.in_ = curr_state
if s.snoop_state.out == SNOOP:
# we wait if we haven't received the response yet
if s.drop & (~s.out.rdy | ~s.in_.en):
s.snoop_state.in_ = WAIT
elif s.snoop_state.out == WAIT:
# we are done waiting if the response arrives
if s.in_.en:
s.snoop_state.in_ = SNOOP
@s.update
def state_output_val():
if s.snoop_state.out == SNOOP:
# if in is enabled, s.in_.rdy and s.out.rdy must be True
s.out.en = s.in_.en & ~s.drop
elif s.snoop_state.out == WAIT:
s.out.en = b1(0)
else:
s.out.en = b1(0)
@s.update
def state_output_rdy():
if s.snoop_state.out == SNOOP:
s.in_.rdy = s.out.rdy
elif s.snoop_state.out == WAIT:
s.in_.rdy = b1(1)
else:
s.in_.rdy = b1(1)
def construct(s):
# Interface
s.recv = RecvIfcRTL(Bits128)
s.send = SendIfcRTL(Bits32)
# Component
s.words = [Wire(Bits16) for _ in range(8)]
s.sum1 = Wire(Bits32)
s.sum2 = Wire(Bits32)
s.in_q = PipeQueueRTL(Bits128, num_entries=1)
s.steps = [StepUnit() for _ in range(8)]
# Register input
connect(s.recv, s.in_q.enq)
# Decompose input message into 8 words
for i in range(8):
s.words[i] //= s.in_q.deq.ret[i * 16:(i + 1) * 16]
# Connect step units
for i in range(8):
s.steps[i].word_in //= s.words[i]
if i == 0:
s.steps[i].sum1_in //= 0
s.steps[i].sum2_in //= 0
else:
s.steps[i].sum1_in //= s.steps[i - 1].sum1_out
s.steps[i].sum2_in //= s.steps[i - 1].sum2_out
s.sum1 //= s.steps[-1].sum1_out
s.sum2 //= s.steps[-1].sum2_out
@update
def up_rtl_send():
go = s.in_q.deq.rdy & s.send.rdy
s.send.en @= go
s.in_q.deq.en @= go
@update
def up_rtl_sum():
s.send.msg @= (s.sum2 << 16) | s.sum1
def construct( s ):
# Interface
s.recv = RecvIfcRTL( Bits128 )
s.send = SendIfcRTL( Bits32 )
# Component
s.words = [ Wire( Bits16 ) for _ in range( 8 ) ]
s.sum1 = Wire( Bits32 )
s.sum2 = Wire( Bits32 )
s.in_q = PipeQueueRTL( Bits128, num_entries=1 )
s.steps = [ StepUnit() for _ in range( 8 ) ]
# Register input
s.connect( s.recv, s.in_q.enq )
# Decompose input message into 8 words
for i in range( 8 ):
s.connect( s.words[i], s.in_q.deq.msg[i*16:(i+1)*16] )
# Connect step units
for i in range( 8 ):
s.connect( s.steps[i].word_in, s.words[i] )
if i == 0:
s.connect( s.steps[i].sum1_in, b32(0) )
s.connect( s.steps[i].sum2_in, b32(0) )
else:
s.connect( s.steps[i].sum1_in, s.steps[i-1].sum1_out )
s.connect( s.steps[i].sum2_in, s.steps[i-1].sum2_out )
s.connect( s.sum1, s.steps[-1].sum1_out )
s.connect( s.sum2, s.steps[-1].sum2_out )
@s.update
def up_rtl_send():
s.send.en = s.in_q.deq.rdy & s.send.rdy
s.in_q.deq.en = s.in_q.deq.rdy & s.send.rdy
@s.update
def up_rtl_sum():
s.send.msg = ( s.sum2 << 16 ) | s.sum1
def construct(s,
DataType,
data_mem_size,
rd_ports=1,
wr_ports=1,
preload_data=[]):
# Constant
AddrType = mk_bits(clog2(data_mem_size))
# Interface
s.recv_raddr = [RecvIfcRTL(AddrType) for _ in range(rd_ports)]
s.send_rdata = [SendIfcRTL(DataType) for _ in range(rd_ports)]
s.recv_waddr = [RecvIfcRTL(AddrType) for _ in range(wr_ports)]
s.recv_wdata = [RecvIfcRTL(DataType) for _ in range(wr_ports)]
# Component
s.sram = [DataType(0, 0) for _ in range(data_mem_size)]
for i in range(len(preload_data)):
s.sram[i] = preload_data[i]
@s.update
def load():
for i in range(rd_ports):
s.send_rdata[i].msg = s.sram[s.recv_raddr[i].msg]
@s.update
def store():
for i in range(wr_ports):
if s.recv_wdata[i].en and s.recv_waddr[i].en:
s.sram[s.recv_waddr[i].msg] = s.recv_wdata[i].msg
@s.update
def update_signal():
for i in range(rd_ports):
s.recv_raddr[i].rdy = s.send_rdata[i].rdy
# b1( 1 ) # s.send_rdata[i].rdy
s.send_rdata[i].en = s.recv_raddr[i].en
# s.send_rdata[i].rdy # s.recv_raddr[i].en
for i in range(wr_ports):
s.recv_waddr[i].rdy = Bits1(1)
s.recv_wdata[i].rdy = Bits1(1)
def construct(s, CtrlType, ctrl_mem_size, num_ctrl=4):
# Constant
# assert( ctrl_mem_size <= num_ctrl )
AddrType = mk_bits(clog2(ctrl_mem_size))
TimeType = mk_bits(clog2(num_ctrl + 1))
last_item = AddrType(ctrl_mem_size - 1)
# Interface
s.send_ctrl = SendIfcRTL(CtrlType)
s.recv_waddr = RecvIfcRTL(AddrType)
s.recv_ctrl = RecvIfcRTL(CtrlType)
# Component
s.reg_file = RegisterFile(CtrlType, ctrl_mem_size, 1, 1)
s.times = Wire(TimeType)
# Connections
s.send_ctrl.msg //= s.reg_file.rdata[0]
s.reg_file.waddr[0] //= s.recv_waddr.msg
s.reg_file.wdata[0] //= s.recv_ctrl.msg
s.reg_file.wen[0] //= s.recv_ctrl.en and s.recv_waddr.en
@s.update
def update_signal():
if s.times == TimeType(
num_ctrl) or s.reg_file.rdata[0].ctrl == OPT_START:
s.send_ctrl.en = b1(0)
else:
s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
s.recv_waddr.rdy = b1(1)
s.recv_ctrl.rdy = b1(1)
@s.update_ff
def update_raddr():
if s.reg_file.rdata[0].ctrl != OPT_START:
if s.times < TimeType(num_ctrl):
s.times <<= s.times + TimeType(1)
if s.reg_file.raddr[0] < last_item:
s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType(1)
else:
s.reg_file.raddr[0] <<= AddrType(0)
def construct(s,
Format,
pkts,
initial_delay=0,
flit_interval_delay=0,
packet_interval_delay=0,
cmp_fn=lambda a, b: a.flits == b.flits):
PhitType = mk_bits(Format.nbits)
s.send = SendIfcRTL(PhitType)
s.src_cl = MflitPacketSourceCL(Format, pkts, initial_delay,
flit_interval_delay,
packet_interval_delay)
s.adapter = RecvCL2SendRTL(PhitType)
connect(s.src_cl.send, s.adapter.recv)
connect(s.adapter.send, s.send)
def construct(s, DataType, num_outports=2):
# Constand
if num_outports == 0:
num_outports = 1
# Interface
s.recv = RecvIfcRTL(DataType)
s.send = [SendIfcRTL(DataType) for _ in range(num_outports)]
@s.update
def update_signal():
s.recv.rdy = s.send[0].rdy
for i in range(num_outports):
s.recv.rdy = s.recv.rdy and s.send[i].rdy
s.send[i].en = s.recv.en
s.send[i].msg = s.recv.msg
def construct(s, PacketType, QueueType=None):
# Local parameter
gating_out = PacketType()
# Interface
s.get = GetIfcRTL(PacketType)
s.send = SendIfcRTL(PacketType)
s.QueueType = QueueType
# If no queue type is assigned
if s.QueueType != None:
# Component
s.queue = QueueType(PacketType)
# Connections
s.get.ret //= s.queue.enq.msg
s.queue.deq.ret //= s.send.msg
@update
def up_get_deq():
both_rdy = s.get.rdy & s.queue.enq.rdy
s.get.en @= both_rdy
s.queue.enq.en @= both_rdy
@update
def up_deq_send():
both_rdy = s.send.rdy & s.queue.deq.rdy
s.send.en @= both_rdy
s.queue.deq.en @= both_rdy
# No ouput queue
else:
s.send.msg //= lambda: s.get.ret if s.send.en else PacketType()
@update
def up_get_send():
both_rdy = s.get.rdy & s.send.rdy
s.get.en @= both_rdy
s.send.en @= both_rdy
def construct(s, DataType, latency = 1 ):
# Constant
s.latency = latency
s.num_entries = 2
s.data = DataType(0, 0)
s.count = OutPort( mk_bits( clog2( s.num_entries+1 ) ) )
# Interface
s.recv = RecvIfcRTL( DataType )
s.send = SendIfcRTL( DataType )
# Component
s.queues = [ NormalQueueRTL( DataType, s.num_entries )
for _ in range( s.latency ) ]
s.count //= s.queues[s.latency - 1].count
@s.update
def process():
if s.recv.msg.bypass == b1( 0 ):
s.recv.rdy = s.queues[0].enq.rdy
s.queues[0].enq.msg = s.recv.msg
s.queues[0].enq.en = s.recv.en and s.queues[0].enq.rdy
for i in range(s.latency - 1):
s.queues[i+1].enq.msg = s.queues[i].deq.ret
s.queues[i+1].enq.en = s.queues[i].deq.rdy and s.queues[i+1].enq.rdy
s.queues[i].deq.en = s.queues[i+1].enq.en
s.send.msg = s.queues[s.latency-1].deq.ret
s.send.en = s.send.rdy and s.queues[s.latency-1].deq.rdy
s.queues[s.latency-1].deq.en = s.send.en
else:
s.send.msg = s.data
s.send.msg.payload = s.recv.msg.payload
s.send.msg.predicate = s.recv.msg.predicate
s.send.msg.bypass = b1( 0 )
s.send.en = s.send.rdy and s.recv.en
s.recv.rdy = s.send.rdy
def construct(s, CtrlType, ctrl_mem_size, num_ctrl=4, opt_list=None, id=0):
# Constant
s.id = id
AddrType = mk_bits(clog2(ctrl_mem_size))
TimeType = mk_bits(clog2(num_ctrl + 1))
# Interface
s.send_ctrl = SendIfcRTL(CtrlType)
# Component
s.sram = [CtrlType(0) for _ in range(ctrl_mem_size)]
for i in range(len(opt_list)):
s.sram[i] = opt_list[i]
s.times = Wire(TimeType)
s.cur = Wire(AddrType)
@s.update
def load():
s.send_ctrl.msg = s.sram[s.cur]
@s.update
def update_signal():
if s.times == TimeType(num_ctrl) or s.sram[
s.cur].ctrl == OPT_START:
s.send_ctrl.en = b1(0)
else:
s.send_ctrl.en = s.send_ctrl.rdy
# if s.id == 6:
# print("[update] tile[", s.id, "] check ctrl out: ", s.send_ctrl.msg, "; send_ctrl.en: ", s.send_ctrl.en, "; send_ctrl.rdy: ", s.send_ctrl.rdy, "; cur: ", s.cur, "; times: ", s.times)
@s.update_ff
def update_raddr():
if s.send_ctrl.rdy:
if s.times < TimeType(num_ctrl):
s.times <<= s.times + TimeType(1)
if s.cur + AddrType(1) == AddrType(num_ctrl):
s.cur <<= AddrType(0)
else:
s.cur <<= s.cur + AddrType(1)
def construct(s, ProcClass, XcelClass):
req_class, resp_class = mk_mem_msg(8, 32, 32)
s.commit_inst = OutPort(Bits1)
# Instruction Memory Request/Response Interface
s.proc = ProcClass()(commit_inst=s.commit_inst)
s.xcel = XcelClass()(xcel=s.proc.xcel)
if isinstance(s.proc.imem, MemMasterIfcRTL): # RTL proc
s.mngr2proc = RecvIfcRTL(Bits32)
s.proc2mngr = SendIfcRTL(Bits32)
s.imem = MemMasterIfcRTL(req_class, resp_class)
s.dmem = MemMasterIfcRTL(req_class, resp_class)
elif isinstance(s.proc.imem, MemMasterIfcCL): # CL proc
s.mngr2proc = NonBlockingCalleeIfc(Bits32)
s.proc2mngr = NonBlockingCallerIfc(Bits32)
s.imem = MemMasterIfcCL(req_class, resp_class)
s.dmem = MemMasterIfcCL(req_class, resp_class)
elif isinstance(s.proc.imem, MemMasterIfcFL): # FL proc
s.mngr2proc = GetIfcFL()
s.proc2mngr = SendIfcFL()
s.imem = MemMasterIfcFL()
s.dmem = MemMasterIfcFL()
s.connect_pairs(
s.mngr2proc,
s.proc.mngr2proc,
s.proc2mngr,
s.proc.proc2mngr,
s.imem,
s.proc.imem,
s.dmem,
s.proc.dmem,
)
def construct( s, DataType, data_mem_size, rd_ports=1, wr_ports=1 ):
# Constant
AddrType = mk_bits( clog2( data_mem_size ) )
# Interface
s.recv_raddr = [ RecvIfcRTL( AddrType ) for _ in range( rd_ports ) ]
s.send_rdata = [ SendIfcRTL( DataType ) for _ in range( rd_ports ) ]
s.recv_waddr = [ RecvIfcRTL( AddrType ) for _ in range( wr_ports ) ]
s.recv_wdata = [ RecvIfcRTL( DataType ) for _ in range( wr_ports ) ]
# Component
s.reg_file = RegisterFile( DataType, data_mem_size, rd_ports, wr_ports )
# Connections
for i in range( rd_ports ):
s.reg_file.raddr[i] //= s.recv_raddr[i].msg
s.send_rdata[i].msg //= s.reg_file.rdata[i]
for i in range( wr_ports ):
s.reg_file.waddr[i] //= s.recv_waddr[i].msg
s.reg_file.wdata[i] //= s.recv_wdata[i].msg
s.reg_file.wen[i] //= s.recv_wdata[i].en and s.recv_waddr[i].en
@s.update
def update_signal():
for i in range( rd_ports ):
s.recv_raddr[i].rdy = s.send_rdata[i].rdy
# b1( 1 ) # s.send_rdata[i].rdy
s.send_rdata[i].en = s.recv_raddr[i].en
# s.send_rdata[i].rdy # s.recv_raddr[i].en
for i in range( wr_ports ):
s.recv_waddr[i].rdy = Bits1( 1 )
s.recv_wdata[i].rdy = Bits1( 1 )
def construct(s, CtrlType, ctrl_mem_size, num_ctrl=4, opt_list=None):
# Constant
AddrType = mk_bits(clog2(ctrl_mem_size))
TimeType = mk_bits(clog2(num_ctrl + 1))
# Interface
s.send_ctrl = SendIfcRTL(CtrlType)
# Component
s.sram = [CtrlType(0) for _ in range(ctrl_mem_size)]
for i in range(len(opt_list)):
s.sram[i] = opt_list[i]
s.times = Wire(TimeType)
s.cur = Wire(AddrType)
@s.update
def load():
s.send_ctrl.msg = s.sram[s.cur]
@s.update
def update_signal():
if s.times == TimeType(num_ctrl) or s.sram[
s.cur].ctrl == OPT_START:
s.send_ctrl.en = b1(0)
else:
s.send_ctrl.en = s.send_ctrl.rdy
@s.update_ff
def update_raddr():
if s.send_ctrl.rdy:
if s.times < TimeType(num_ctrl):
s.times <<= s.times + TimeType(1)
if s.cur + AddrType(1) == AddrType(num_ctrl):
s.cur <<= AddrType(0)
else:
s.cur <<= s.cur + AddrType(1)
