def construct(s, ProcClass, XcelClass):
req_class, resp_class = mk_mem_msg(8, 32, 32)
s.commit_inst = OutPort(Bits1)
# Instruction Memory Request/Response Interface
s.proc = ProcClass()
s.proc.commit_inst //= s.commit_inst
s.xcel = XcelClass()
s.xcel.xcel //= s.proc.xcel
if isinstance(s.proc.imem, MemMasterIfcRTL): # RTL proc
s.mngr2proc = RecvIfcRTL(Bits32)
s.proc2mngr = SendIfcRTL(Bits32)
s.imem = MemMasterIfcRTL(req_class, resp_class)
s.dmem = MemMasterIfcRTL(req_class, resp_class)
elif isinstance(s.proc.imem, MemMasterIfcCL): # CL proc
s.mngr2proc = CalleeIfcCL(Type=Bits32)
s.proc2mngr = CallerIfcCL(Type=Bits32)
s.imem = MemMasterIfcCL(req_class, resp_class)
s.dmem = MemMasterIfcCL(req_class, resp_class)
elif isinstance(s.proc.imem, MemMasterIfcFL): # FL proc
s.mngr2proc = GetIfcFL(Type=Bits32)
s.proc2mngr = SendIfcFL(Type=Bits32)
s.imem = MemMasterIfcFL()
s.dmem = MemMasterIfcFL()
s.mngr2proc //= s.proc.mngr2proc
s.proc2mngr //= s.proc.proc2mngr
s.imem //= s.proc.imem
s.dmem //= s.proc.dmem
def construct(s, Req, Resp, id, num_requesters, num_responders):
# Local parameter
assert num_requesters > 0
assert num_responders > 0
assert has_field(Req, 'opaque')
assert has_field(Resp, 'opaque')
src_nbits = 1 if num_requesters == 1 else clog2(num_requesters)
dst_nbits = 1 if num_responders == 1 else clog2(num_responders)
OpaqueT = get_field_type(Resp, 'opaque')
SrcT = mk_bits(src_nbits)
DstT = mk_bits(dst_nbits)
assert src_nbits <= OpaqueT.nbits, \
f'opaque field of {Resp.__qualname__} has only {OpaqueT.nbits} bits ' \
f'but {src_nbits} bits is needed for src id!'
sl_src = slice(0, src_nbits)
s.id = DstT(id)
NetReq = mk_req_msg(Req, num_responders)
NetResp = mk_resp_msg(Resp, num_requesters)
# Interface
s.minion = MemMinionIfcRTL(NetReq, NetResp)
s.master = MemMasterIfcRTL(Req, Resp)
# Logic
s.minion.req.rdy //= s.master.req.rdy
s.minion.resp.en //= s.master.resp.en
s.master.req.en //= s.minion.req.en
s.master.resp.rdy //= s.minion.resp.rdy
@update
def up_master_req_msg():
s.master.req.msg @= s.minion.req.msg.payload
@update
def up_minion_resp_msg():
s.minion.resp.msg.dst @= s.master.resp.msg.opaque[sl_src]
s.minion.resp.msg.payload @= s.master.resp.msg
def construct(s,
Req,
Resp,
num_requesters,
num_responders,
max_req_in_flight=2,
DstLogicT=DstLogicSingleResp):
# Local parameter
NetReq = mk_req_msg(Req, num_responders)
NetResp = mk_resp_msg(Resp, num_requesters)
# Interface
s.minion = [MemMinionIfcRTL(Req, Resp) for _ in range(num_requesters)]
s.master = [MemMasterIfcRTL(Req, Resp) for _ in range(num_responders)]
# Component
s.req_net = XbarRTL(NetReq, num_requesters, num_responders)
s.resp_net = XbarRTL(NetResp, num_responders, num_requesters)
s.req_adapter = [
ReqAdapter(Req, Resp, i, num_requesters, num_responders,
max_req_in_flight, DstLogicT)
for i in range(num_requesters)
]
s.resp_adapter = [
RespAdapter(Req, Resp, i, num_requesters, num_responders)
for i in range(num_responders)
]
# Connections
for i in range(num_requesters):
s.req_adapter[i].minion //= s.minion[i]
s.req_adapter[i].master.req //= s.req_net.recv[i]
s.req_adapter[i].master.resp //= s.resp_net.send[i]
for i in range(num_responders):
s.resp_adapter[i].minion.req //= s.req_net.send[i]
s.resp_adapter[i].minion.resp //= s.resp_net.recv[i]
s.resp_adapter[i].master //= s.master[i]
def construct( s ):
req_class, resp_class = mk_mem_msg( 8, 32, 32 )
# Proc/Mngr Interface
s.mngr2proc = RecvIfcRTL( Bits32 )
s.proc2mngr = SendIfcRTL( Bits32 )
# Instruction Memory Request/Response Interface
s.imem = MemMasterIfcRTL( req_class, resp_class )
# Data Memory Request/Response Interface
s.dmem = MemMasterIfcRTL( req_class, resp_class )
# Xcel Request/Response Interface
xreq_class, xresp_class = mk_xcel_msg( 5, 32 )
s.xcel = XcelMasterIfcRTL( xreq_class, xresp_class )
# val_W port used for counting commited insts.
s.commit_inst = OutPort( Bits1 )
# Bypass queues
s.imemreq_q = BypassQueue2RTL( req_class, 2 )
# We have to turn input receive interface into get interface
s.imemresp_q = BypassQueueRTL( resp_class, 1 )
s.dmemresp_q = BypassQueueRTL( resp_class, 1 )
s.mngr2proc_q = BypassQueueRTL( Bits32, 1 )
s.xcelresp_q = BypassQueueRTL( xresp_class, 1 )
# imem drop unit
s.imemresp_drop = m = DropUnitRTL( Bits32 )
m.in_.en //= s.imemresp_q.deq.en
m.in_.rdy //= s.imemresp_q.deq.rdy
m.in_.ret //= s.imemresp_q.deq.ret.data
# connect all the queues
s.imemreq_q.deq //= s.imem.req
s.imemresp_q.enq //= s.imem.resp
s.dmemresp_q.enq //= s.dmem.resp
s.mngr2proc_q.enq //= s.mngr2proc
s.xcelresp_q.enq //= s.xcel.resp
# Control
s.ctrl = m = ProcCtrl()
# imem port
m.imemresp_drop //= s.imemresp_drop.drop
m.imemreq_en //= s.imemreq_q.enq.en
m.imemreq_rdy //= s.imemreq_q.enq.rdy
m.imemresp_en //= s.imemresp_drop.out.en
m.imemresp_rdy //= s.imemresp_drop.out.rdy
# dmem port
m.dmemreq_en //= s.dmem.req.en
m.dmemreq_rdy //= s.dmem.req.rdy
m.dmemreq_type //= s.dmem.req.msg.type_
m.dmemresp_en //= s.dmemresp_q.deq.en
m.dmemresp_rdy //= s.dmemresp_q.deq.rdy
# xcel port
m.xcelreq_type //= s.xcel.req.msg.type_
m.xcelreq_en //= s.xcel.req.en
m.xcelreq_rdy //= s.xcel.req.rdy
m.xcelresp_en //= s.xcelresp_q.deq.en
m.xcelresp_rdy //= s.xcelresp_q.deq.rdy
# proc2mngr and mngr2proc
m.proc2mngr_en //= s.proc2mngr.en
m.proc2mngr_rdy //= s.proc2mngr.rdy
m.mngr2proc_en //= s.mngr2proc_q.deq.en
m.mngr2proc_rdy //= s.mngr2proc_q.deq.rdy
# commit inst for counting
m.commit_inst //= s.commit_inst
# Dpath
s.dpath = m = ProcDpath()
# imem ports
m.imemreq_addr //= s.imemreq_q.enq.msg.addr
m.imemresp_data //= s.imemresp_drop.out.ret
# dmem ports
m.dmemreq_addr //= s.dmem.req.msg.addr
m.dmemreq_data //= s.dmem.req.msg.data
m.dmemresp_data //= s.dmemresp_q.deq.ret.data
# xcel ports
m.xcelreq_addr //= s.xcel.req.msg.addr
m.xcelreq_data //= s.xcel.req.msg.data
m.xcelresp_data //= s.xcelresp_q.deq.ret.data
# mngr
m.mngr2proc_data //= s.mngr2proc_q.deq.ret
m.proc2mngr_data //= s.proc2mngr.msg
# Ctrl <-> Dpath
s.ctrl.reg_en_F //= s.dpath.reg_en_F
s.ctrl.pc_sel_F //= s.dpath.pc_sel_F
s.ctrl.reg_en_D //= s.dpath.reg_en_D
s.ctrl.op1_byp_sel_D //= s.dpath.op1_byp_sel_D
s.ctrl.op2_byp_sel_D //= s.dpath.op2_byp_sel_D
s.ctrl.op2_sel_D //= s.dpath.op2_sel_D
s.ctrl.imm_type_D //= s.dpath.imm_type_D
s.ctrl.reg_en_X //= s.dpath.reg_en_X
s.ctrl.alu_fn_X //= s.dpath.alu_fn_X
s.ctrl.reg_en_M //= s.dpath.reg_en_M
s.ctrl.wb_result_sel_M //= s.dpath.wb_result_sel_M
s.ctrl.reg_en_W //= s.dpath.reg_en_W
s.ctrl.rf_waddr_W //= s.dpath.rf_waddr_W
s.ctrl.rf_wen_W //= s.dpath.rf_wen_W
s.dpath.inst_D //= s.ctrl.inst_D
s.dpath.ne_X //= s.ctrl.ne_X
def construct(s,
Req,
Resp,
id,
num_requesters,
num_responders,
max_req_in_flight=2,
DstLogicT=DstLogicSingleResp):
# Local parameters
assert num_requesters > 0
assert num_responders > 0
assert has_field(Req, 'opaque')
assert has_field(Resp, 'opaque')
src_nbits = 1 if num_requesters == 1 else clog2(num_requesters)
dst_nbits = 1 if num_responders == 1 else clog2(num_responders)
idx_nbits = 1 if max_req_in_flight == 1 else clog2(max_req_in_flight)
OpaqueT = get_field_type(Req, 'opaque')
SrcT = mk_bits(src_nbits)
DstT = mk_bits(dst_nbits)
IdxT = mk_bits(idx_nbits)
assert src_nbits + idx_nbits <= OpaqueT.nbits, \
f'opaque field of {Req.__qualname__} has only {OpaqueT.nbits} bits ' \
f'but {src_nbits} bits is needed for src id and {idx_nbits} for ROB index!'
sl_src = slice(0, src_nbits)
sl_idx = slice(src_nbits, src_nbits + idx_nbits)
NetReq = mk_req_msg(Req, num_responders)
NetResp = mk_resp_msg(Resp, num_requesters)
# Interface
s.minion = MemMinionIfcRTL(Req, Resp)
s.master = MemMasterIfcRTL(NetReq, NetResp)
# Opaque table
s.opq_table = Table(OpaqueT, max_req_in_flight)
s.opq_table.alloc.en //= s.minion.req.en
s.opq_table.alloc.msg //= s.minion.req.msg.opaque
s.opq_table.dealloc.en //= s.master.resp.en
s.opq_table.dealloc.msg //= s.master.resp.msg.payload.opaque[sl_idx]
# Destination logic
s.dst_logic = DstLogicT(Req, SrcT, DstT)
s.dst_logic.in_req //= s.minion.req.msg
s.dst_logic.in_src_id //= id
# Logic
s.minion.req.rdy //= lambda: s.opq_table.alloc.rdy & s.master.req.rdy
s.minion.resp.en //= lambda: s.master.resp.en
s.master.req.en //= lambda: s.minion.req.en
s.master.resp.rdy //= lambda: s.minion.resp.rdy
@update
def up_master_req_msg():
s.master.req.msg.dst @= s.dst_logic.out_dst
s.master.req.msg.payload @= s.minion.req.msg
s.master.req.msg.payload.opaque[sl_src] @= id
s.master.req.msg.payload.opaque[sl_idx] @= s.opq_table.alloc.ret
@update
def up_minion_resp_msg():
s.minion.resp.msg @= s.master.resp.msg.payload
s.minion.resp.msg.opaque @= s.opq_table.dealloc.ret