def test_demux_8way(self):
for in_, *selectors in list(product([True, False], repeat=4)):
out = demux_8way(in_, selectors)
a, b, c, d, e, f, g, h = (False, ) * 8
if in_:
if selectors[2]:
if selectors[1]:
if selectors[0]:
a = True
else:
b = True
else:
if selectors[0]:
c = True
else:
d = True
else:
if selectors[1]:
if selectors[0]:
e = True
else:
f = True
else:
if selectors[0]:
g = True
else:
h = True
self.assertEqual((a, b, c, d, e, f, g, h), out)
def ram_8(in_: Bool16, load: bool, address: Bool3) -> Bool16:
"""Memory using 8 16-bit registers"""
load_a, load_b, load_c, load_d, load_e, load_f, load_g, load_h = demux_8way(
load, address)
return mux_16_8way(address, reg_a(in_, load_a), reg_b(in_, load_b),
reg_c(in_, load_c), reg_d(in_, load_d),
reg_e(in_, load_e), reg_f(in_, load_f),
reg_g(in_, load_g), reg_h(in_, load_h))
def ram_4k(in_: Bool16, load: bool, address: Bool12) -> Bool16:
"""Memory using 4096 16-bit registers."""
load_a, load_b, load_c, load_d, load_e, load_f, load_g, load_h = demux_8way(
load, address[0:3])
return mux_16_8way(address, ram_512_a(in_, load_a, address[3:12]),
ram_512_b(in_, load_b, address[3:12]),
ram_512_c(in_, load_c, address[3:12]),
ram_512_d(in_, load_d, address[3:12]),
ram_512_e(in_, load_e, address[3:12]),
ram_512_f(in_, load_f, address[3:12]),
ram_512_g(in_, load_g, address[3:12]),
ram_512_h(in_, load_h, address[3:12]))
def ram_512(in_: Bool16, load: bool, address: Bool9) -> Bool16:
"""Memory using 512 16-bit registers."""
load_a, load_b, load_c, load_d, load_e, load_f, load_g, load_h = demux_8way(
load, address[0:3])
return mux_16_8way(address, ram_64_a(in_, load_a, address[3:9]),
ram_64_b(in_, load_b, address[3:9]),
ram_64_c(in_, load_c, address[3:9]),
ram_64_d(in_, load_d, address[3:9]),
ram_64_e(in_, load_e, address[3:9]),
ram_64_f(in_, load_f, address[3:9]),
ram_64_g(in_, load_g, address[3:9]),
ram_64_h(in_, load_h, address[3:9]))
def ram_64(in_: Bool16, load: bool, address: Bool6) -> Bool16:
"""Memory using 64 16-bit registers"""
load_a, load_b, load_c, load_d, load_e, load_f, load_g, load_h = demux_8way(
load, address[0:3])
return mux_16_8way(address, ram_8_a(in_, load_a, address[3:6]),
ram_8_b(in_, load_b, address[3:6]),
ram_8_c(in_, load_c, address[3:6]),
ram_8_d(in_, load_d, address[3:6]),
ram_8_e(in_, load_e, address[3:6]),
ram_8_f(in_, load_f, address[3:6]),
ram_8_g(in_, load_g, address[3:6]),
ram_8_h(in_, load_h, address[3:6]))