示例#1
0
文件: vhdl.py 项目: peteut/migen
def _printnode_assign(node, ctx):
    at = get("at", ctx)
    if R.isinstance(Cat, node.l):
        return pipe(
            node.l.l,
            reversed,
            map(juxt([identity, len])),
            list,
            juxt([identity, comp(sum, map(second))]),
            juxt([first,
                  comp(reduce(partial(accumulate, sub)),
                       juxt([comp(map(second), first),
                             second]))]),
            R.apply(zip),
            map(lambda x: _printnode(
                x[0][0].eq(node.r[x[1] - x[0][1]: x[1]]), ctx)),
            ";\n".join)

    lhs = _printexpr(node.l, merge(ctx,
                                   dict(lhs=True,
                                        thint=_THint.logic,
                                        lhint=None)))
    rhs = _printexpr(node.r, merge(ctx,
                                   dict(
                                       lhs=False,
                                       thint=_THint.logic,
                                       lhint=len(node.l)
                                       if R.isinstance(Constant, node.r) or
                                       len(node.l) > len(node.r)
                                       else None)))

    return pipe([lhs, ":=" if at == _AT_BLOCKING else "<=", rhs], " ".join)
示例#2
0
文件: vhdl.py 项目: peteut/migen
def _printnode_assign(node, ctx):
    at = get("at", ctx)
    if R.isinstance(Cat, node.l):
        return pipe(
            node.l.l, reversed, map(juxt([identity, len])), list,
            juxt([identity, comp(sum, map(second))]),
            juxt([
                first,
                comp(reduce(partial(accumulate, sub)),
                     juxt([comp(map(second), first), second]))
            ]), R.apply(zip),
            map(lambda x: _printnode(x[0][0].eq(node.r[x[1] - x[0][1]:x[1]]),
                                     ctx)), ";\n".join)

    lhs = _printexpr(
        node.l, merge(ctx, dict(lhs=True, thint=_THint.logic, lhint=None)))
    rhs = _printexpr(
        node.r,
        merge(
            ctx,
            dict(lhs=False,
                 thint=_THint.logic,
                 lhint=len(node.l) if R.isinstance(Constant, node.r)
                 or len(node.l) > len(node.r) else None)))

    return pipe([lhs, ":=" if at == _AT_BLOCKING else "<=", rhs], " ".join)
示例#3
0
文件: vhdl.py 项目: peteut/migen
def _printgeneric(param, ns):
    from migen.fhdl.specials import Instance

    if R.isinstance(Instance.PreformattedParam, param):
        return param

    raise NotImplementedError("{} not implemented".format(type(param)))
示例#4
0
文件: vhdl.py 项目: peteut/migen
def _printgeneric(param, ns):
    from migen.fhdl.specials import Instance

    if R.isinstance(Instance.PreformattedParam, param):
        return param

    raise NotImplementedError("{} not implemented".format(type(param)))
示例#5
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文件: vhdl.py 项目: peteut/migen
def convert(f,
            ios=None,
            name="top",
            special_overrides=dict(),
            attr_translate=None,
            create_clock_domains=True,
            display_run=False,
            asic_syntax=False):
    r = ConvOutput()
    if R.complement(R.isinstance(_Fragment))(f):
        f = f.get_fragment()
    if ios is None:
        ios = set()

    for cd_name in sorted(list_clock_domains(f)):
        try:
            f.clock_domains[cd_name]
        except KeyError:
            if create_clock_domains:
                cd = ClockDomain(cd_name)
                f.clock_domains.append(cd)
                ios |= {cd.clk, cd.rst}
            else:
                raise KeyError("Unresolved clock domain: '{}'".format(cd_name))

    f = lower_complex_slices(f)
    insert_resets(f)
    f = lower_basics(f)
    fs, lowered_specials = lower_specials(special_overrides, f.specials)
    f += lower_basics(fs)

    ns = build_namespace(
        list_signals(f) | list_special_ios(f, True, True, True) | ios,
        _reserved_keywords)
    ns.clock_domains = f.clock_domains
    r.ns = ns
    specials = f.specials - lowered_specials
    r.set_main_source("".join([
        _printentity(f, ios, name, ns),
        _printarchitecture(f, ios, name, ns, special_overrides, specials,
                           r.add_data_file)
    ]))

    return r
示例#6
0
文件: vhdl.py 项目: peteut/migen
def convert(f, ios=None, name="top",
            special_overrides=dict(),
            attr_translate=None,
            create_clock_domains=True,
            display_run=False,
            asic_syntax=False):
    r = ConvOutput()
    if R.complement(R.isinstance(_Fragment))(f):
        f = f.get_fragment()
    if ios is None:
        ios = set()

    for cd_name in sorted(list_clock_domains(f)):
        try:
            f.clock_domains[cd_name]
        except KeyError:
            if create_clock_domains:
                cd = ClockDomain(cd_name)
                f.clock_domains.append(cd)
                ios |= {cd.clk, cd.rst}
            else:
                raise KeyError("Unresolved clock domain: '{}'".format(cd_name))

    f = lower_complex_slices(f)
    insert_resets(f)
    f = lower_basics(f)
    fs, lowered_specials = lower_specials(special_overrides, f.specials)
    f += lower_basics(fs)

    ns = build_namespace(
        list_signals(f) | list_special_ios(f, True, True, True) | ios,
        _reserved_keywords)
    ns.clock_domains = f.clock_domains
    r.ns = ns
    specials = f.specials - lowered_specials
    r.set_main_source("".join([
        _printentity(f, ios, name, ns),
        _printarchitecture(
            f, ios, name, ns, special_overrides, specials, r.add_data_file)]))

    return r
示例#7
0
    if isinstance(data, dict) and lang in data:
        return data[lang]
    return data


def localize2(lang, data):
    localize_one_level_on_lang = lambda x: localize_one_level(lang, x)
    return cata(localize_one_level_on_lang, data)


val = {
    "en": "This is a sentence in english",
    "fr": "Ceci est une phrase en français"
}

tagfn = lambda fn: r.if_else(r.isinstance(bs4.element.Tag), fn, r.identity)
scalarfn = lambda fn: r.if_else(r.isinstance(list), r.identity,
                                maybe_none_resolver)

data = cata(tagfn(me.find_all('tr')), at3)
data2 = cata(tagfn(me.find_all('td')), data)
data_texts = cata(tagfn(mn.get_text()), data2)
data3 = cata(tagfn(mn.find('a')), data2)
data_titles = cata(tagfn(mn.get('title')), data3)
data_links = cata(tagfn(mn.get('href')), data3)
#data5 = cata(tagfn(maybe_none_resolver),data4)

uw_titles = cata(lambda x: x.value
                 if isinstance(x, md.Maybe) else x, data_titles)
uw_texts = cata(lambda x: x.value
                if isinstance(x, md.Maybe) else x, data_texts)
示例#8
0
文件: mn.py 项目: flintc/sandbox
    # def bind(self,fn):
    #     return super(Result,self).bind( r.compose(r.if_else(r.isinstance(Exception),Error,Result),excepting( fn ) ) )
    def map(self, fn):
        return Result(fn(self.value))

    def chain(self, fn):
        return fn(self.value)

    def __add__(self, other):
        return Result(self.value +
                      other.value) if not isinstance(other, Error) else self


#Result = md.Result

ex = MethodAp(lambda x: x, r.if_else(r.isinstance(Exception), Error, Result),
              excepting)
em = MethodAp(lambda x: x,
              r.if_else(lambda x: len(x) == 0, r.always(Nothing), Just))
en = MethodAp(lambda x: x,
              r.if_else(lambda x: x is None, r.always(Nothing), Just))
p = MethodAp(lambda x: x, lambda x: x)
itex = IterableAp(lambda x: x, r.if_else(r.isinstance(Exception), Error,
                                         Result), excepting)
item = IterableAp(lambda x: x,
                  r.if_else(lambda x: len(x) == 0, r.always(Nothing), Just))
iten = IterableAp(lambda x: x,
                  r.if_else(lambda x: x is None, r.always(Nothing), Just))
it = IterableAp(lambda x: x, lambda x: x)
sc = ScalarAp(lambda x: x, lambda x: x)
scex = ScalarAp(lambda x: x, r.if_else(r.isinstance(Exception), Error, Result),
示例#9
0
文件: vhdl.py 项目: peteut/migen
def _printexpr_operator(node, ctx):
    thint = get("thint", ctx)
    arity = len(node.operands)
    if arity == 1:
        r1 = _printexpr(node.operands[0],
                        merge(ctx, dict(lhs=False,
                                        thint=_THint.logic,
                                        lhint=None)))
        if node.op == "-":
            expr = "(-{})".format(_signed(r1))
            if thint == _THint.un_signed:
                return expr
            elif thint == _THint.integer:
                return _to_integer(expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr
        else:
            expr = "{} {}".format(_get_op(node), r1)
            if thint == _THint.un_signed:
                return _unsigned(expr)
            elif thint == _THint.integer:
                return _fn_call("to_integer", _unsigned(expr))
            elif thint == _THint.boolean:
                return _fn_call("\\??\\", expr)
            else:
                return "({})".format(expr)
    elif arity == 2:
        if _is_bitwise_op(node):
            r1, r2 = pipe(
                [node, ctx],
                juxt([
                    comp(attrgetter("operands"), first),
                    comp(repeat, flip(merge, dict(lhs=False,
                                                  thint=_THint.logic,
                                                  lhint=None)), second),
                ]), R.apply(zip), map(R.apply(_printexpr)))
            expr = pipe([r1, _get_op(node), r2], " ".join)
            if thint == _THint.un_signed:
                return _unsigned(expr)
            elif thint == _THint.integer:
                return _fn_call("to_integer", expr)
            else:
                return expr
        elif _is_comp_op(node):
            if pipe(node.operands, R.all_satisfy(comp(R.equals(1), len))):
                r1, r2 = pipe(
                    [node, ctx],
                    juxt([
                        comp(attrgetter("operands"), first),
                        comp(repeat, flip(merge, dict(lhs=False,
                                                      thint=_THint.logic,
                                                      lhint=None)), second),
                    ]), R.apply(zip), R.map(R.apply(_printexpr)))
            else:
                r1, r2 = pipe(
                    [node, ctx],
                    juxt([
                        comp(attrgetter("operands"), first),
                        comp(repeat, second)]), R.apply(zip),
                    map(juxt([
                        first,
                        comp(
                            R.apply(merge),
                            juxt([
                                second,
                                R.always(dict(lhs=False, lhint=None)),
                                R.if_else(
                                    comp(R.isinstance(Constant), first),
                                    R.always(dict(thint=_THint.integer)),
                                    R.always(dict(thint=_THint.un_signed)))
                            ]))])),
                    map(R.apply(_printexpr)))
            if thint == _THint.logic:
                return _fn_call(pipe(node, _get_op, "\\?{}\\".format), r1, r2)
            else:
                return pipe([r1, _get_op(node), r2], " ".join)
        elif _is_shift_op(node):
            r1, r2 = pipe(
                [node, ctx],
                juxt([
                    comp(attrgetter("operands"), first),
                    comp(repeat, second)]), R.apply(zip),
                map(juxt([
                    first,
                    comp(
                        R.apply(merge),
                        juxt([
                            second,
                            R.always(dict(lhs=False, lhint=None)),
                            R.if_else(
                                comp(R.isinstance(Constant), first),
                                R.always(dict(thint=_THint.integer)),
                                R.always(dict(thint=_THint.un_signed)))
                        ]))])),
                map(R.apply(_printexpr)))
            expr = _fn_call(_shift_op[node.op], r1, r2)
            if thint == _THint.integer:
                return _fn_call("to_integer", expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr
        elif _is_arith_op(node):
            r1, r2 = pipe(
                node.operands,
                map(lambda x:
                    _printexpr(x,
                               merge(ctx,
                                     dict(lhs=False,
                                          thint=_THint.integer
                                          if R.isinstance(Constant, x)
                                          else _THint.un_signed,
                                          lhint=None)))))
            expr = pipe([r1, _arith_op_map[node.op], r2], " ".join)
            if thint == _THint.integer:
                return _fn_call("to_integer", expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr

    raise TypeError("unkown operator: {}, arity: {}".format(node, arity))
示例#10
0
文件: vhdl.py 项目: peteut/migen
def _is_op_cmp(node):
    return node.op == "==" if R.isinstance(_Operator, node) else False
示例#11
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文件: vhdl.py 项目: peteut/migen

_get_comb, _get_sync, _get_clock_domains = map(
    attrgetter, ["comb", "sync", "clock_domains"])

_r_name = "{}_r".format

_v_name = "{}_v".format

_sorted_sync = comp(concatv, partial(sorted, key=get(0)), iteritems, _get_sync)

_cd_regs = comp(
    map(juxt([
        first,
        comp(list, filter(complement(is_variable)),
             filter(comp(R.isinstance(Signal))), list_targets, second)])),
    _sorted_sync)

_assignment_filter_fn = comp(
    R.apply(and_), juxt([
        comp(R.equals(1), len, first),
        comp(R.isinstance(_Assign), get_in([1, 0]))]))

_comb = comp(concatv, group_by_targets, _get_comb)

_assignments = comp(map(get_in([1, 0])), filter(_assignment_filter_fn), _comb)

_comb_statements = comp(pluck(1), _comb)

# _comb_sigs = comp(concat, pluck(0), _comb)
示例#12
0
文件: vhdl.py 项目: peteut/migen
def _printexpr_operator(node, ctx):
    thint = get("thint", ctx)
    arity = len(node.operands)
    if arity == 1:
        r1 = _printexpr(
            node.operands[0],
            merge(ctx, dict(lhs=False, thint=_THint.logic, lhint=None)))
        if node.op == "-":
            expr = "(-{})".format(_signed(r1))
            if thint == _THint.un_signed:
                return expr
            elif thint == _THint.integer:
                return _to_integer(expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr
        else:
            expr = "{} {}".format(_get_op(node), r1)
            if thint == _THint.un_signed:
                return _unsigned(expr)
            elif thint == _THint.integer:
                return _fn_call("to_integer", _unsigned(expr))
            elif thint == _THint.boolean:
                return _fn_call("\\??\\", expr)
            else:
                return "({})".format(expr)
    elif arity == 2:
        if _is_bitwise_op(node):
            r1, r2 = pipe([node, ctx],
                          juxt([
                              comp(attrgetter("operands"), first),
                              comp(
                                  repeat,
                                  flip(
                                      merge,
                                      dict(lhs=False,
                                           thint=_THint.logic,
                                           lhint=None)), second),
                          ]), R.apply(zip), map(R.apply(_printexpr)))
            expr = pipe([r1, _get_op(node), r2], " ".join)
            if thint == _THint.un_signed:
                return _unsigned(expr)
            elif thint == _THint.integer:
                return _fn_call("to_integer", expr)
            else:
                return expr
        elif _is_comp_op(node):
            if pipe(node.operands, R.all_satisfy(comp(R.equals(1), len))):
                r1, r2 = pipe([node, ctx],
                              juxt([
                                  comp(attrgetter("operands"), first),
                                  comp(
                                      repeat,
                                      flip(
                                          merge,
                                          dict(lhs=False,
                                               thint=_THint.logic,
                                               lhint=None)), second),
                              ]), R.apply(zip), R.map(R.apply(_printexpr)))
            else:
                r1, r2 = pipe(
                    [node, ctx],
                    juxt([
                        comp(attrgetter("operands"), first),
                        comp(repeat, second)
                    ]), R.apply(zip),
                    map(
                        juxt([
                            first,
                            comp(
                                R.apply(merge),
                                juxt([
                                    second,
                                    R.always(dict(lhs=False, lhint=None)),
                                    R.if_else(
                                        comp(R.isinstance(Constant), first),
                                        R.always(dict(thint=_THint.integer)),
                                        R.always(dict(thint=_THint.un_signed)))
                                ]))
                        ])), map(R.apply(_printexpr)))
            if thint == _THint.logic:
                return _fn_call(pipe(node, _get_op, "\\?{}\\".format), r1, r2)
            else:
                return pipe([r1, _get_op(node), r2], " ".join)
        elif _is_shift_op(node):
            r1, r2 = pipe(
                [node, ctx],
                juxt([
                    comp(attrgetter("operands"), first),
                    comp(repeat, second)
                ]), R.apply(zip),
                map(
                    juxt([
                        first,
                        comp(
                            R.apply(merge),
                            juxt([
                                second,
                                R.always(dict(lhs=False, lhint=None)),
                                R.if_else(
                                    comp(R.isinstance(Constant), first),
                                    R.always(dict(thint=_THint.integer)),
                                    R.always(dict(thint=_THint.un_signed)))
                            ]))
                    ])), map(R.apply(_printexpr)))
            expr = _fn_call(_shift_op[node.op], r1, r2)
            if thint == _THint.integer:
                return _fn_call("to_integer", expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr
        elif _is_arith_op(node):
            r1, r2 = pipe(
                node.operands,
                map(lambda x: _printexpr(
                    x,
                    merge(
                        ctx,
                        dict(lhs=False,
                             thint=_THint.integer if R.isinstance(Constant, x)
                             else _THint.un_signed,
                             lhint=None)))))
            expr = pipe([r1, _arith_op_map[node.op], r2], " ".join)
            if thint == _THint.integer:
                return _fn_call("to_integer", expr)
            elif thint == _THint.logic:
                return _std_logic_vector(expr)
            else:
                return expr

    raise TypeError("unkown operator: {}, arity: {}".format(node, arity))
示例#13
0
文件: vhdl.py 项目: peteut/migen
def _is_op_cmp(node):
    return node.op == "==" if R.isinstance(_Operator, node) else False
示例#14
0
文件: vhdl.py 项目: peteut/migen
_get_comb, _get_sync, _get_clock_domains = map(
    attrgetter, ["comb", "sync", "clock_domains"])

_r_name = "{}_r".format

_v_name = "{}_v".format

_sorted_sync = comp(concatv, partial(sorted, key=get(0)), iteritems, _get_sync)

_cd_regs = comp(
    map(
        juxt([
            first,
            comp(list, filter(complement(is_variable)),
                 filter(comp(R.isinstance(Signal))), list_targets, second)
        ])), _sorted_sync)

_assignment_filter_fn = comp(
    R.apply(and_),
    juxt([
        comp(R.equals(1), len, first),
        comp(R.isinstance(_Assign), get_in([1, 0]))
    ]))

_comb = comp(concatv, group_by_targets, _get_comb)

_assignments = comp(map(get_in([1, 0])), filter(_assignment_filter_fn), _comb)

_comb_statements = comp(pluck(1), _comb)