def __init__(
self,
dev='/dev/datadev_0',
):
super().__init__(name='ePixHr10kT', description='ePixHrGen1 board')
self.dmaCtrlStreams = [None]
self.dmaCtrlStreams[0] = rogue.hardware.axi.AxiStreamDma(
dev, (0x100 * 0) + 0, 1) # Registers
# Create and Connect SRP to VC1 to send commands
self._srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.dmaCtrlStreams[0], self._srp)
self.add(
epixHr.SysReg(
name='Core',
memBase=self._srp,
offset=0x00000000,
sim=False,
expand=False,
pgpVersion=4,
))
self.add(
fpga.EpixHR10kT(name='EpixHR',
memBase=self._srp,
offset=0x80000000,
hidden=False,
enabled=True))
def __init__(self,
*,
ipAddr='10.0.0.1',
name='base',
description='',
**kwargs):
pyrogue.Root.__init__(self,
name=name,
description=description,
**kwargs)
# Create SRP/ASYNC_MSG interface
self.rudp = pyrogue.protocols.UdpRssiPack(name='rudpReg',
host=ipAddr,
port=8193,
packVer=1,
jumbo=False)
# Connect the SRPv3 to tDest = 0x0
self.srp = rogue.protocols.srp.SrpV3()
pyrogue.streamConnectBiDir(self.srp, self.rudp.application(dest=0x0))
# Create stream interface
self.stream = pyrogue.protocols.UdpRssiPack(name='rudpData',
host=ipAddr,
port=8194,
packVer=1,
jumbo=False)
def __init__(self,
*,
ip_addr="",
config_file=None,
epics_prefix="EpicsPrefix",
polling_en=True,
pv_dump_file="",
disable_bay0=False,
disable_bay1=False,
txDevice=None,
configure=False,
server_port=0,
**kwargs):
# Create Interleaved RSSI interface
self._stream = pyrogue.protocols.UdpRssiPack(name='rudp',
host=ip_addr,
port=8198,
packVer=2,
jumbo=True)
# Connect the SRPv3 to tDest = 0x0
self._srp = rogue.protocols.srp.SrpV3()
pyrogue.streamConnectBiDir(self._srp,
self._stream.application(dest=0x0))
# Instantiate Fpga top level
self._fpga = FpgaTopLevel(
memBase=self._srp,
ipAddr=ip_addr,
commType="eth-rssi-interleaved",
pcieRssiLink=0, # Not needed
disableBay0=disable_bay0,
disableBay1=disable_bay1)
# Create stream interfaces
self._ddr_streams = []
# DDR streams. The FpgaTopLevel class will defined a 'stream' interface exposing them.
# We are only using the first 2 channel of each AMC daughter card, i.e. channels 0, 1, 4, 5.
for i in [0, 1, 4, 5]:
self._ddr_streams.append(self._stream.application(0x80 + i))
# Streaming interface stream. It comes over UDP, port 8195, without RSSI,
# so we an UdpReceiver.
self._streaming_stream = pysmurf.core.devices.UdpReceiver(
ip_addr=ip_addr, port=8195)
# Setup base class
Common.__init__(self,
config_file=config_file,
epics_prefix=epics_prefix,
polling_en=polling_en,
pv_dump_file=pv_dump_file,
txDevice=txDevice,
configure=configure,
server_port=server_port,
**kwargs)
def __init__(self,
*,
pcie_rssi_lane=0,
pcie_dev_rssi="/dev/datadev_0",
pcie_dev_data="/dev/datadev_1",
config_file=None,
epics_prefix="EpicsPrefix",
polling_en=True,
pv_dump_file="",
disable_bay0=False,
disable_bay1=False,
txDevice=None,
configure=False,
server_port=0,
**kwargs):
# TDEST 0 routed to streamr0 (SRPv3)
self.dma = rogue.hardware.axi.AxiStreamDma(
pcie_dev_rssi, (pcie_rssi_lane * 0x100 + 0), True)
self.srp = rogue.protocols.srp.SrpV3()
pyrogue.streamConnectBiDir(self.srp, self.dma)
# Instantiate Fpga top level
self._fpga = FpgaTopLevel(memBase=self.srp,
ipAddr="",
commType="pcie-rssi-interleaved",
pcieRssiLink=pcie_rssi_lane,
disableBay0=disable_bay0,
disableBay1=disable_bay1)
# Create stream interfaces
self._ddr_streams = []
# DDR streams. We are only using the first 2 channel of each AMC daughter card, i.e.
# channels 0, 1, 4, 5.
for i in [0, 1, 4, 5]:
self._ddr_streams.append(
rogue.hardware.axi.AxiStreamDma(
pcie_dev_rssi, (pcie_rssi_lane * 0x100 + 0x80 + i), True))
# Streaming interface stream
self._streaming_stream = \
rogue.hardware.axi.AxiStreamDma(pcie_dev_data,(pcie_rssi_lane*0x100 + 0xC1), True)
# Setup base class
Common.__init__(self,
config_file=config_file,
epics_prefix=epics_prefix,
polling_en=polling_en,
pv_dump_file=pv_dump_file,
txDevice=txDevice,
configure=configure,
server_port=server_port,
**kwargs)
def __init__(self):
pyrogue.Root.__init__(self,name='evalBoard',description='Evaluation Board')
# File writer
dataWriter = pyrogue.utilities.fileio.StreamWriter(name='dataWriter')
self.add(dataWriter)
# Create the PGP interfaces
udp = pyrogue.protocols.UdpRssiPack(host='192.168.2.194',port=8192,size=1400)
# Create and Connect SRP to VC0
srp = rogue.protocols.srp.SrpV3()
pyrogue.streamConnectBiDir(srp,udp.application(0))
# Add configuration stream to file as channel 0
pyrogue.streamConnect(self,dataWriter.getChannel(0x0))
pyrogue.streamConnect(udp.application(1),dataWriter.getChannel(0x1))
# PRBS Receiver as secdonary receiver for VC1
#prbsRx = pyrogue.utilities.prbs.PrbsRx('prbsRx')
#pyrogue.streamTap(udp.application(1),prbsRx)
#self.add(prbsRx)
# Add Devices
self.add(surf.axi.AxiVersion(memBase=srp,offset=0x0,expand=False))
#self.add(surf.protocols.ssi.SsiPrbsTx(memBase=srp,offset=0x40000))
self.add(pyrogue.LocalVariable(name='list',value=([0] * 10)))
self.smem = pyrogue.smem.SMemControl(group='rogueTest',root=self)
# Run control
self.add(pyrogue.RunControl(name='runControl' ,
rates={1:'1 Hz', 10:'10 Hz',30:'30 Hz'}))
#cmd=self.SsiPrbsTx.oneShot()))
# Export remote objects
#self.start(pollEn=True,pyroGroup='rogueTest',pyroHost='134.79.229.11',pyroNs='134.79.229.11')
#self.start(pollEn=True,pyroGroup='rogueTest',pyroHost='134.79.229.11')
#self.start(pollEn=True,pyroGroup='rogueTest')
self.start(pollEn=True,pyroGroup='rogueTest')
# Create epics node
pvMap = {'evalBoard.AxiVersion.UpTimeCnt':'testCnt',
'evalBoard.AxiVersion.ScratchPad':'testPad'}
pvMap = None # Comment out to enable map
self.epics = pyrogue.epics.EpicsCaServer(base='rogueTest',root=self,pvMap=pvMap)
self.epics.start()
self.mysql = pyrogue.mysql.MysqlGw(dbHost='localhost',dbName='rogue',dbUser='******',dbPass='******',root=self)
self.mysql.start()
def __init__(
self,
name='ClinkDev',
description='Container for CameraLink Dev',
dev='/dev/datadev_0', # path to PCIe device
version3=False, # true = PGPv3, false = PGP2b
pollEn=False, # Enable automatic polling registers
initRead=True, # Read all registers at start of the system
numLane=1, # Number of PGP lanes
**kwargs):
super().__init__(name=name,
description=description,
dev=dev,
version3=version3,
pollEn=pollEn,
initRead=initRead,
numLane=numLane,
**kwargs)
# Check if not doing simulation
if (dev != 'sim'):
# Create arrays to be filled
self._srp = [None for lane in range(numLane)]
# Create the stream interface
for lane in range(numLane):
# SRP
self._srp[lane] = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self._dma[lane][0], self._srp[lane])
# CameraLink Feb Board
self.add(
feb.ClinkFeb(
name=(f'ClinkFeb[{lane}]'),
memBase=self._srp[lane],
version3=version3,
enableDeps=[
self.Hardware.PgpMon[lane].RxRemLinkReady
], # Only allow access if the PGP link is established
# expand = False,
))
# Start the system
self.start(
pollEn=self._pollEn,
initRead=self._initRead,
timeout=self._timeout,
)
def __init__(self, *, ipAddr='10.0.0.1', name='base', description = '', **kwargs):
pyrogue.Root.__init__(self, name=name, description=description, **kwargs)
self.srp=pyrogue.interfaces.simulation.MemEmulate()
# UDP only
self.udp = rogue.protocols.udp.Client(ipAddr,8192,0)
# Connect the SRPv0 to RAW UDP
self.srp = rogue.protocols.srp.SrpV0()
pyrogue.streamConnectBiDir( self.srp, self.udp )
self.stream = None
# Top level module should be added here.
# Top level is a sub-class of AmcCarrierCore.AppTop.TopLevel
# SRP interface should be passed as an arg
self.add(FpgaTopLevel(memBase=self.srp))
def __init__(self,
*,
ipAddr='10.0.0.1',
name='base',
description='',
**kwargs):
pyrogue.Root.__init__(self,
name=name,
description=description,
**kwargs)
# Create Interleaved RSSI interface
self.rudp = self.stream = pyrogue.protocols.UdpRssiPack(name='rudp',
host=ipAddr,
port=8198,
packVer=2,
jumbo=True)
# Connect the SRPv3 to tDest = 0x0
self.srp = rogue.protocols.srp.SrpV3()
pyrogue.streamConnectBiDir(self.srp, self.rudp.application(dest=0x0))
def __init__(self,
name="Top",
description="Container for FPGA",
hwEmu=False,
rssiEn=False,
ip='192.168.1.10',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# Check if emulating the GUI interface
if (hwEmu):
# Create emulated hardware interface
print("Running in Hardware Emulation Mode:")
srp = pyrogue.interfaces.simulation.MemEmulate()
else:
# Create srp interface
srp = rogue.protocols.srp.SrpV3()
# Check for RSSI
if (rssiEn):
# UDP + RSSI
udp = pyrogue.protocols.UdpRssiPack(host=ip,
port=8192,
size=1500)
# Connect the SRPv3 to tDest = 0x0
pyrogue.streamConnectBiDir(srp, udp.application(dest=0x0))
else:
# UDP only
udp = rogue.protocols.udp.Client(ip, 8192, 1500)
# Connect the SRPv3 to UDP
pyrogue.streamConnectBiDir(srp, udp)
self.add(board.Fpga(
memBase=srp,
offset=0x00000000,
))
def __init__(
self,
dataDebug=False,
dev='/dev/datadev_0', # path to PCIe device
enLclsI=True,
enLclsII=False,
startupMode=False, # False = LCLS-I timing mode, True = LCLS-II timing mode
standAloneMode=False, # False = using fiber timing, True = locally generated timing
pgp3=False, # true = PGPv3, false = PGP2b
pollEn=True, # Enable automatic polling registers
initRead=True, # Read all registers at start of the system
numLanes=4, # Number of PGP lanes
camType=None,
defaultFile=None,
enableDump=False,
clDevTarget=clDev.ClinkDevKcu1500,
**kwargs):
# Set the firmware Version lock = firmware/targets/shared_version.mk
self.FwVersionLock = 0x04090000
# Set number of lanes to min. requirement
if numLanes > len(camType):
laneSize = len(camType)
else:
laneSize = numLanes
# Set local variables
self.camType = [camType[i] for i in range(laneSize)]
self.defaultFile = defaultFile
self.dev = dev
self.startupMode = startupMode
self.standAloneMode = standAloneMode
self.enableDump = enableDump
# Check for simulation
if dev == 'sim':
kwargs['timeout'] = 100000000 # 100 s
else:
kwargs['timeout'] = 5000000 # 5 s
# Pass custom value to parent via super function
super().__init__(dev=dev,
pgp3=pgp3,
pollEn=pollEn,
initRead=initRead,
numLanes=laneSize,
**kwargs)
# Unhide the RemoteVariableDump command
self.RemoteVariableDump.hidden = False
# Create memory interface
self.memMap = axipcie.createAxiPcieMemMap(dev, 'localhost', 8000)
self.memMap.setName('PCIe_Bar0')
# Instantiate the top level Device and pass it the memory map
self.add(
clDevTarget(
name='ClinkPcie',
memBase=self.memMap,
numLanes=laneSize,
pgp3=pgp3,
enLclsI=enLclsI,
enLclsII=enLclsII,
expand=True,
))
# CLink SRP, CLink serial
destList = [0, 2]
# Create DMA streams
self.dmaStreams = axipcie.createAxiPcieDmaStreams(
dev,
{lane: {dest
for dest in destList}
for lane in range(laneSize)}, 'localhost', 8000)
# Check if not doing simulation
if (dev != 'sim'):
# Create arrays to be filled
self._srp = [None for lane in range(laneSize)]
# Create the stream interface
for lane in range(laneSize):
# SRP
self._srp[lane] = rogue.protocols.srp.SrpV3()
self._srp[lane].setName(f'SRPv3[{lane}]')
pr.streamConnectBiDir(self.dmaStreams[lane][0],
self._srp[lane])
# CameraLink Feb Board
self.add(
feb.ClinkFeb(
name=(f'ClinkFeb[{lane}]'),
memBase=self._srp[lane],
serial=self.dmaStreams[lane][2],
camType=self.camType[lane],
version3=pgp3,
enableDeps=[
self.ClinkPcie.Hsio.PgpMon[lane].RxRemLinkReady
], # Only allow access if the PGP link is established
expand=True,
))
# Else doing Rogue VCS simulation
else:
self.roguePgp = shared.RogueStreams(numLanes=laneSize, pgp3=pgp3)
# Create arrays to be filled
self._frameGen = [None for lane in range(laneSize)]
# Create the stream interface
for lane in range(laneSize):
# Create the frame generator
self._frameGen[lane] = MyCustomMaster()
# Connect the frame generator
print(self.roguePgp.pgpStreams)
self._frameGen[lane] >> self.roguePgp.pgpStreams[lane][1]
# Create a command to execute the frame generator
self.add(
pr.BaseCommand(
name=f'GenFrame[{lane}]',
function=lambda cmd, lane=lane: self._frameGen[lane].
myFrameGen(),
))
# Create a command to execute the frame generator. Accepts user data argument
self.add(
pr.BaseCommand(
name=f'GenUserFrame[{lane}]',
function=lambda cmd, lane=lane: self._frameGen[lane].
myFrameGen,
))
# Create arrays to be filled
self._dbg = [None for lane in range(laneSize)]
self.unbatchers = [
rogue.protocols.batcher.SplitterV1() for lane in range(laneSize)
]
# Create the stream interface
for lane in range(laneSize):
# Debug slave
if dataDebug:
# Connect the streams
self.dmaStreams[lane][1] >> self.unbatchers[lane] >> self._dbg[
lane]
self.add(
pr.LocalVariable(
name='RunState',
description=
'Run state status, which is controlled by the StopRun() and StartRun() commands',
mode='RO',
value=False,
))
@self.command(
description='Stops the triggers and blows off data in the pipeline'
)
def StopRun():
print('ClinkDev.StopRun() executed')
# Get devices
eventBuilder = self.find(typ=batcher.AxiStreamBatcherEventBuilder)
trigger = self.find(typ=l2si.TriggerEventBuffer)
# Turn off the triggering
for devPtr in trigger:
devPtr.MasterEnable.set(False)
# Flush the downstream data/trigger pipelines
for devPtr in eventBuilder:
devPtr.Blowoff.set(True)
# Update the run state status variable
self.RunState.set(False)
@self.command(
description=
'starts the triggers and allow steams to flow to DMA engine')
def StartRun():
print('ClinkDev.StartRun() executed')
# Get devices
eventBuilder = self.find(typ=batcher.AxiStreamBatcherEventBuilder)
trigger = self.find(typ=l2si.TriggerEventBuffer)
# Reset all counters
self.CountReset()
# Arm for data/trigger stream
for devPtr in eventBuilder:
devPtr.Blowoff.set(False)
devPtr.SoftRst()
# Turn on the triggering
for devPtr in trigger:
devPtr.MasterEnable.set(True)
# Update the run state status variable
self.RunState.set(True)
def __init__(self,
*,
pcie_rssi_lane=0,
pcie_dev_rssi="/dev/datadev_0",
pcie_dev_data="/dev/datadev_1",
config_file=None,
epics_prefix="EpicsPrefix",
polling_en=True,
pv_dump_file="",
disable_bay0=False,
disable_bay1=False,
enable_pwri2c=False,
txDevice=None,
configure=False,
VariableGroups=None,
server_port=0,
**kwargs):
# TDEST 0 routed to streamr0 (SRPv3)
self._srpStream = rogue.hardware.axi.AxiStreamDma(
pcie_dev_rssi, (pcie_rssi_lane * 0x100 + 0), True)
# Create the SRP Engine
self._srp = rogue.protocols.srp.SrpV3()
pyrogue.streamConnectBiDir(self._srp, self._srpStream)
# Instantiate Fpga top level
# In order to be backwards compatible for now, also support
# FpgaTopLevel which doesn't have the enablePwrI2C argument.
try:
self._fpga = FpgaTopLevel(memBase=self._srp,
disableBay0=disable_bay0,
disableBay1=disable_bay1,
enablePwrI2C=enable_pwri2c)
except TypeError as e:
print(f"TypeError calling FpgaTopLevel: {e}")
print(
"This FpgaTopLevel does not support the option 'enablePwrI2C'."
)
print("Please use a pyrogue zip file which is up to date.")
print(
"Staring the server without using the 'enablePwrI2C' option.")
self._fpga = FpgaTopLevel(memBase=self._srp,
disableBay0=disable_bay0,
disableBay1=disable_bay1)
# Create stream interfaces
self._ddr_streams = []
# DDR streams. We are only using the first 2 channel of each AMC daughter card, i.e.
# channels 0, 1, 4, 5.
for i in [0, 1, 4, 5]:
tmp = rogue.hardware.axi.AxiStreamDma(
pcie_dev_rssi, (pcie_rssi_lane * 0x100 + 0x80 + i), True)
tmp.setZeroCopyEn(False)
self._ddr_streams.append(tmp)
# Streaming interface stream
self._streaming_stream = \
rogue.hardware.axi.AxiStreamDma(pcie_dev_data,(pcie_rssi_lane*0x100 + 0xC1), True)
# Setup base class
Common.__init__(self,
config_file=config_file,
epics_prefix=epics_prefix,
polling_en=polling_en,
pv_dump_file=pv_dump_file,
txDevice=txDevice,
configure=configure,
VariableGroups=VariableGroups,
server_port=server_port,
**kwargs)
def __init__( self,
name = "MyRoot",
description = "my root container",
type = 'datadev',
dev = '/dev/datadev_0',
ip = '192.168.2.10',
lane = 0,
enPrbs = True,
fpgaType = '',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
#################################################################
# DataDev PCIe Card (used for PGP PCIe applications)
if ( type == 'datadev' ):
self.vc0Srp = rogue.hardware.axi.AxiStreamDma(dev,(lane*0x100)+0,True)
self.vc1Prbs = rogue.hardware.axi.AxiStreamDma(dev,(lane*0x100)+1,True)
# RUDP Ethernet
elif ( type == 'eth' ):
# Create the ETH interface @ IP Address = ip
self.rudp = pr.protocols.UdpRssiPack(
host = ip,
port = 8192,
packVer = 2,
jumbo = True,
expand = False,
)
self.add(self.rudp)
# Map the AxiStream.TDEST
self.vc0Srp = self.rudp.application(0); # AxiStream.tDest = 0x0
self.vc1Prbs = self.rudp.application(1); # AxiStream.tDest = 0x1
# Undefined device type
else:
raise ValueError("Invalid type (%s)" % (type) )
#################################################################
# Connect VC0 to SRPv3
self.srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.vc0Srp,self.srp)
if enPrbs:
# Connect VC1 to FW TX PRBS
self.prbsRx = pyrogue.utilities.prbs.PrbsRx(name='PrbsRx',width=128,expand=False)
pyrogue.streamConnect(self.vc1Prbs,self.prbsRx)
self.add(self.prbsRx)
# Connect VC1 to FW RX PRBS
self.prbTx = pyrogue.utilities.prbs.PrbsTx(name="PrbsTx",width=128,expand=False)
pyrogue.streamConnect(self.prbTx, self.vc1Prbs)
self.add(self.prbTx)
else:
pyrogue.streamConnect(self.vc1Prbs,self.vc1Prbs)
# Add registers
self.add(devBoard.Fpga(
memBase = self.srp,
commType = type,
fpgaType = fpgaType,
expand = True,
))
def __init__(self):
pyrogue.Root.__init__(self, 'evalBoard', 'Evaluation Board')
# File writer
dataWriter = pyrogue.utilities.fileio.StreamWriter('dataWriter')
self.add(dataWriter)
# Create the PGP interfaces
pgpVc0 = rogue.hardware.pgp.PgpCard('/dev/pgpcard_0', 0,
0) # Registers
pgpVc1 = rogue.hardware.pgp.PgpCard('/dev/pgpcard_0', 0, 1) # Data
pgpVc3 = rogue.hardware.pgp.PgpCard('/dev/pgpcard_0', 0,
3) # Microblaze
print("")
print("PGP Card Version: %x" % (pgpVc0.getInfo().version))
# Create and Connect SRP to VC0
srp = rogue.protocols.srp.SrpV0()
pyrogue.streamConnectBiDir(pgpVc0, srp)
# Add configuration stream to file as channel 0
pyrogue.streamConnect(self, dataWriter.getChannel(0x0))
# Add data stream to file as channel 1
pyrogue.streamConnect(pgpVc1, dataWriter.getChannel(0x1))
## Add microblaze console stream to file as channel 2
pyrogue.streamConnect(pgpVc3, dataWriter.getChannel(0x2))
# PRBS Receiver as secdonary receiver for VC1
prbsRx = pyrogue.utilities.prbs.PrbsRx('prbsRx')
pyrogue.streamTap(pgpVc1, prbsRx)
self.add(prbsRx)
# Microblaze console monitor add secondary tap
mbcon = MbDebug()
pyrogue.streamTap(pgpVc3, mbcon)
# Add Devices
self.add(surf.axi.AxiVersion(memBase=srp, offset=0x0))
self.add(surf.protocols.ssi.SsiPrbsTx(memBase=srp, offset=0x30000))
self.smem = pyrogue.smem.SMemControl(group='rogueTest', root=self)
# Run control
self.add(
pyrogue.RunControl(name='runControl',
rates={
1: '1 Hz',
10: '10 Hz',
30: '30 Hz'
}))
#cmd=self.SsiPrbsTx.oneShot()))
# Export remote objects
self.start(pyroGroup='rogueTest')
# Create epics node
pvMap = {
'evalBoard.AxiVersion.UpTimeCnt': 'testCnt',
'evalBoard.AxiVersion.ScratchPad': 'testPad'
}
pvMap = None # Comment out to enable map
self.epics = pyrogue.epics.EpicsCaServer(base='rogueTest',
root=self,
pvMap=pvMap)
self.epics.start()
def __init__( self,
name = 'FpgaTopLevel',
description = 'Container for FPGA Top-Level',
# Communication Parameters
simGui = False,
commType = 'eth-rssi-non-interleaved',
ipAddr = '10.0.1.101',
pcieDev = '/dev/datadev_0',
pcieRssiLink = 0,
# JESD Parameters
numRxLanes = [0,0],
numTxLanes = [0,0],
enJesdDrp = False,
# Signal Generator Parameters
numSigGen = [0,0],
sizeSigGen = [0,0],
modeSigGen = [False,False],
# General Parameters
enableBsa = False,
enableMps = False,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
self._numRxLanes = numRxLanes
self._numTxLanes = numTxLanes
rssiInterlaved = False
rssiNotInterlaved = False
# Check for valid link range
if (pcieRssiLink<0) or (pcieRssiLink>5):
raise ValueError("Invalid pcieRssiLink (%d)" % (pcieRssiLink) )
if (simGui):
# Create simulation srp interface
srp=pyrogue.interfaces.simulation.MemEmulate()
else:
################################################################################################################
# UDP_SRV_XVC_IDX_C => 2542, -- Xilinx XVC
# UDP_SRV_SRPV0_IDX_C => 8192, -- Legacy SRPv0 register access (still used for remote FPGA reprogramming)
# UDP_SRV_RSSI0_IDX_C => 8193, -- Legacy Non-interleaved RSSI for Register access and ASYNC messages
# UDP_SRV_RSSI1_IDX_C => 8194, -- Legacy Non-interleaved RSSI for bulk data transfer
# UDP_SRV_BP_MGS_IDX_C => 8195, -- Backplane Messaging
# UDP_SRV_TIMING_IDX_C => 8197, -- Timing ASYNC Messaging
# UDP_SRV_RSSI_ILEAVE_IDX_C => 8198); -- Interleaved RSSI
################################################################################################################
if ( commType=="eth-fsbl" ):
# UDP only
udp = rogue.protocols.udp.Client(ipAddr,8192,0)
# Connect the SRPv0 to RAW UDP
srp = rogue.protocols.srp.SrpV0()
pyrogue.streamConnectBiDir( srp, udp )
elif ( commType=="eth-rssi-non-interleaved" ):
# Update the flag
rssiNotInterlaved = True
# Create SRP/ASYNC_MSG interface
rudp = pyrogue.protocols.UdpRssiPack( name='rudpReg', host=ipAddr, port=8193, packVer = 1)
# Connect the SRPv3 to tDest = 0x0
srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir( srp, rudp.application(dest=0x0) )
# Create stream interface
self.stream = pr.protocols.UdpRssiPack( name='rudpData', host=ipAddr, port=8194, packVer = 1)
elif ( commType=="eth-rssi-interleaved" ):
# Update the flag
rssiInterlaved = True
# Create Interleaved RSSI interface
rudp = self.stream = pyrogue.protocols.UdpRssiPack( name='rudp', host=ipAddr, port=8198, packVer = 2)
self.add(rudp)
# Connect the SRPv3 to tDest = 0x0
srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir( srp, rudp.application(dest=0x0) )
# Connect SRPv3 to DDR on tDest = 0x4
srpDdr = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir( srpDdr, rudp.application(dest=0x4) )
elif ( commType == 'pcie-fsbl' ):
# Connect the SRPv0 to tDest = 0x0
vc0Srp = rogue.hardware.axi.AxiStreamDma(pcieDev,(pcieRssiLink*3)+0,1)
srp = rogue.protocols.srp.SrpV0()
pr.streamConnectBiDir( srp, vc0Srp )
elif ( commType == 'pcie-rssi-interleaved' ):
# Update the flag
rssiInterlaved = True
#########################################################################################
# Assumes this PCIe card Configuration:
#########################################################################################
# constant NUM_LINKS_C : positive := 1;
# constant RSSI_PER_LINK_C : positive := 6;
# constant RSSI_STREAMS_C : positive := 3;
# constant AXIS_PER_LINK_C : positive := RSSI_PER_LINK_C*RSSI_STREAMS_C;
# constant NUM_AXIS_C : positive := NUM_LINKS_C*AXIS_PER_LINK_C;
# constant NUM_RSSI_C : positive := NUM_LINKS_C*RSSI_PER_LINK_C;
#########################################################################################
#########################################################################################
# Assumes this RSSI Wrapper TDEST Mapping:
#########################################################################################
# APP_STREAM_ROUTES_G => (
# 0 => X"00", -- TDEST 0 routed to stream 0 (SRPv3)
# 1 => "10------", -- TDEST x80-0xBF routed to stream 1 (Raw Data)
# 2 => "11------"), -- TDEST 0xC0-0xFF routed to stream 2 (Application)
#########################################################################################
# Connect the SRPv3 to tDest = 0x0
vc0Srp = rogue.hardware.axi.AxiStreamDma(pcieDev,(pcieRssiLink*3)+0,1)
srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir( srp, vc0Srp )
# Create the Raw Data stream interface (TDEST x80-0xBF routed to stream 1 (Raw Data))
self.streamVc0 = rogue.hardware.axi.AxiStreamDma(pcieDev,(pcieRssiLink*3)+1,1)
# Create the Raw Data stream interface (TDEST xC0-0xFF routed to stream 2 (Raw Data))
self.streamVc1 = rogue.hardware.axi.AxiStreamDma(pcieDev,(pcieRssiLink*3)+2,1)
#########################################################################################
# Note: (pcieRssiLink*3)+2 <--> TDEST 0xC0-0xFF routed to stream 2 (Application)
# not include in this device and assumed to be attached to c++ or python in separate code
#########################################################################################
# Undefined device type
else:
raise ValueError("Invalid type (%s)" % (commType) )
# Add devices
self.add(AmcCarrierCore(
memBase = srp,
offset = 0x00000000,
rssiInterlaved = rssiInterlaved,
rssiNotInterlaved = rssiNotInterlaved,
enableBsa = enableBsa,
enableMps = enableMps,
))
# self.add(AppTop(
# memBase = srp,
# offset = 0x80000000,
# numRxLanes = numRxLanes,
# numTxLanes = numTxLanes,
# enJesdDrp = enJesdDrp,
# numSigGen = numSigGen,
# sizeSigGen = sizeSigGen,
# modeSigGen = modeSigGen,
# ))
self.add(pr.Device(
name = 'DDR',
memBase = srpDdr,
offset = 0x00000000,
size = 0x10000000,
))
# Define SW trigger command
@self.command(description="Software Trigger for DAQ MUX",)
def SwDaqMuxTrig():
pass
# Get the arguments
args = parser.parse_args()
#################################################################
# Set base
base = pr.Root(name='simulation', description='Simple RogueSim Example')
# Connect the SRPv3 stream port
srpStream = pr.interfaces.simulation.StreamSim(host='localhost',
dest=0,
uid=1,
ssi=True)
memMap = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(memMap, srpStream)
# Add devices
base.add(
axiVer.AxiVersion(
name='AxiVersion',
memBase=memMap,
offset=0x00000000,
expand=False,
))
# Start the system
base.start(
pollEn=args.pollEn,
initRead=args.initRead,
timeout=1.0,
def __init__(self,
name='TopLevel',
description='Container for FPGA Top-Level',
dev0='/dev/datadev_0',
dev1='/dev/datadev_1',
lane=0,
ip=None,
loopback=False,
swRx=True,
swTx=True,
allLane=False,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
if ip is not None:
self.rudp = pr.protocols.UdpRssiPack(
host=ip,
port=8198,
packVer=2,
jumbo=True,
expand=False,
)
# self.add(self.rudp)
self.vc0Srp = self.rudp.application(0)
# AxiStream.tDest = 0x0
self.vc1Prbs = self.rudp.application(1)
# AxiStream.tDest = 0x1
# TDEST 0 routed to stream 0 (SRPv3)
self.srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.vc0Srp, self.srp)
if (loopback):
# Loopback the PRBS data
pr.streamConnect(self.vc1Prbs, self.vc1Prbs)
else:
if (swTx):
# Connect VC1 to FW RX PRBS
self.prbTx = pr.utilities.prbs.PrbsTx(name="PrbsTx",
width=128,
expand=False)
pr.streamConnect(self.prbTx, self.vc1Prbs)
self.add(self.prbTx)
if (swRx):
# Connect VC1 to FW TX PRBS
self.prbsRx = pr.utilities.prbs.PrbsRx(name='PrbsRx',
width=128,
expand=True)
pr.streamConnect(self.vc1Prbs, self.prbsRx)
self.add(self.prbsRx)
self.add(Fpga(
memBase=self.srp,
expand=True,
))
# Add registers
elif allLane != 0:
self.vc0Srp = [None for i in range(6)]
self.vc1Prbs = [None for i in range(6)]
self.srp = [None for i in range(6)]
self.prbsTx = [None for i in range(6)]
self.prbsRx = [None for i in range(6)]
for i in range(allLane):
self.vc0Srp[i] = rogue.hardware.axi.AxiStreamDma(
dev0, (i * 0x100) + 0, True)
# self.vc1Prbs[i] = rogue.hardware.axi.AxiStreamDma(dev1,(i*0x100)+1,True)
self.vc1Prbs[i] = rogue.hardware.axi.AxiStreamDma(
dev1, (i * 0x100) + 0xC1, True)
self.srp[i] = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.vc0Srp[i], self.srp[i])
self.add(Fpga(
name=f'Fpga[{i}]',
memBase=self.srp[i],
))
if (loopback):
# Loopback the PRBS data
pr.streamConnect(self.vc1Prbs[i], self.vc1Prbs[i])
else:
if (swTx):
# Connect VC1 to FW RX PRBS
self.prbsTx[i] = pr.utilities.prbs.PrbsTx(
name=f'PrbsTx[{i}]', width=128, expand=False)
pr.streamConnect(self.prbsTx[i], self.vc1Prbs[i])
self.add(self.prbsTx[i])
if (swRx):
# Connect VC1 to FW TX PRBS
self.prbsRx[i] = pr.utilities.prbs.PrbsRx(
name=f'PrbsRx[{i}]', width=128, expand=True)
pr.streamConnect(self.vc1Prbs[i], self.prbsRx[i])
self.add(self.prbsRx[i])
else:
self.vc0Srp = rogue.hardware.axi.AxiStreamDma(
dev0, (lane * 0x100) + 0, True)
# self.vc1Prbs = rogue.hardware.axi.AxiStreamDma(dev1,(lane*0x100)+1,True)
self.vc1Prbs = rogue.hardware.axi.AxiStreamDma(
dev1, (lane * 0x100) + 0xC1, True)
# TDEST 0 routed to stream 0 (SRPv3)
self.srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.vc0Srp, self.srp)
if (loopback):
# Loopback the PRBS data
pr.streamConnect(self.vc1Prbs, self.vc1Prbs)
else:
if (swTx):
# Connect VC1 to FW RX PRBS
self.prbTx = pr.utilities.prbs.PrbsTx(name="PrbsTx[0]",
width=128,
expand=False)
pr.streamConnect(self.prbTx, self.vc1Prbs)
self.add(self.prbTx)
if (swRx):
# Connect VC1 to FW TX PRBS
self.prbsRx = pr.utilities.prbs.PrbsRx(name='PrbsRx[0]',
width=128,
expand=True)
pr.streamConnect(self.vc1Prbs, self.prbsRx)
self.add(self.prbsRx)
self.add(Fpga(
name='Fpga[0]',
memBase=self.srp,
))
(34 * 0) + 2 * 1) # VC1
pgpL0Vc2 = rogue.interfaces.stream.TcpClient('localhost', simPort +
(34 * 0) + 2 * 2) # VC2
pgpL0Vc3 = rogue.interfaces.stream.TcpClient('localhost', simPort +
(34 * 0) + 2 * 3) # VC3
pgpL2Vc0 = rogue.interfaces.stream.TcpClient('localhost', simPort +
(34 * 2) + 2 * 0) # L2VC0
pgpL3Vc0 = rogue.interfaces.stream.TcpClient('localhost', simPort +
(34 * 3) + 2 * 0) # L3VC0
elif (args.type == 'dataFile'):
print("Bypassing hardware.")
else:
raise ValueError("Invalid type (%s)" % (args.type))
'''
##########
#added connect vco to srp? use the eth arguements
##########
# Connect VC0 to SRPv3
srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(vc0Srp,srp)
if args.enPrbs:
# Connect VC1 to FW TX PRBS
prbsRx = pyrogue.utilities.prbs.PrbsRx(name='PrbsRx',width=128,expand=False)
pyrogue.streamConnect(vc1Prbs,prbsRx)
#self.add(prbsRx)
def __init__(self,
dataDebug = False,
dev = '/dev/datadev_0',# path to PCIe device
pgp3 = True, # true = PGPv3, false = PGP2b
pollEn = True, # Enable automatic polling registers
initRead = True, # Read all registers at start of the system
defaultFile = None,
hwType = None,
**kwargs):
# Set the min. firmware Versions
self.PcieVersion = 0x04000000
self.FebVersion = 0x04000000
# Set local variables
self.defaultFile = defaultFile
self.dev = dev
kwargs['timeout'] = 5000000 # 5 s
devTarget = None
numPgpLanes = 0
numTimingLanes = 0
if hwType == 'DrpPgpTDet':
devTarget = l2si_drp.DrpPgpTDet
numPgpLanes = 1
numTimingLanes = 1
numDmaLanes = numPgpLanes + numTimingLanes
# Pass custom value to parent via super function
super().__init__(
dev = dev,
pgp3 = pgp3,
pollEn = pollEn,
initRead = initRead,
numLanes = numDmaLanes,
**kwargs)
# Create memory interface
self.memMap = axipcie.createAxiPcieMemMap(dev, 'localhost', 8000)
# Instantiate the top level Device and pass it the memory map
self.add(devTarget(
name = 'PgpPcie',
memBase = self.memMap,
numPgpLanes = numPgpLanes,
numTimingLanes = numTimingLanes,
pgp3 = pgp3,
expand = True,
))
# Create DMA streams
vcs = [0,1,2] if dataDebug else [0,2]
self.dmaStreams = axipcie.createAxiPcieDmaStreams(dev, {lane:{dest for dest in vcs} for lane in range(numDmaLanes)}, 'localhost', 8000)
# Check if not doing simulation
if (dev!='sim'):
# Create arrays to be filled
self._srp = [None for lane in range(numPgpLanes)]
# Create the stream interface
for lane in range(numPgpLanes):
# SRP
self._srp[lane] = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.dmaStreams[lane][0],self._srp[lane])
# CameraLink Feb Board
self.add(feb.ClinkFeb(
name = (f'ClinkFeb[{lane}]'),
memBase = self._srp[lane],
serial = self.dmaStreams[lane][2],
camType = self.camType[lane],
version3 = pgp3,
enableDeps = [self.ClinkPcie.Hsio.PgpMon[lane].RxRemLinkReady], # Only allow access if the PGP link is established
expand = True,
))
# Create arrays to be filled
self._dbg = [None for lane in range(numPgpLanes)]
self.unbatchers = [rogue.protocols.batcher.SplitterV1() for lane in range(numPgpLanes)]
# Create the stream interface
for lane in range(numPgpLanes):
# Debug slave
if dataDebug:
# Connect the streams
#self.dmaStreams[lane][1] >> self.unbatchers[lane] >> self._dbg[lane]
self.dmaStreams[lane][1] >> self.unbatchers[lane]
self.add(pr.LocalVariable(
name = 'RunState',
description = 'Run state status, which is controlled by the StopRun() and StartRun() commands',
mode = 'RO',
value = False,
))
def __init__(
self,
name='ClinkDev',
description='Container for CameraLink Dev',
dev='/dev/datadev_0', # path to PCIe device
version3=False, # true = PGPv3, false = PGP2b
pollEn=True, # Enable automatic polling registers
initRead=True, # Read all registers at start of the system
numLane=4, # Number of PGP lanes
camType=['Opal000', None],
defaultFile=None,
**kwargs):
super().__init__(name=name,
description=description,
dev=dev,
version3=version3,
numLane=numLane,
**kwargs)
self.defaultFile = defaultFile
# Set the min. firmware Versions
self.minPcieVersion = 0x01000200
self.minFebVersion = 0x01000200
# PGP Application on PCIe
self.add(
app.Application(
memBase=self._memMap,
numLane=numLane,
expand=True,
))
# Check if not doing simulation
if (dev != 'sim'):
# Create arrays to be filled
self._srp = [None for lane in range(numLane)]
# Create the stream interface
for lane in range(numLane):
# SRP
self._srp[lane] = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self._dma[lane][0], self._srp[lane])
# CameraLink Feb Board
self.add(
feb.ClinkFeb(
name=(f'ClinkFeb[{lane}]'),
memBase=self._srp[lane],
serial=[self._dma[lane][2], self._dma[lane][3]],
camType=camType,
version3=version3,
enableDeps=[
self.Hardware.PgpMon[lane].RxRemLinkReady
], # Only allow access if the PGP link is established
expand=False,
))
# Else doing Rogue VCS simulation
else:
# Create arrays to be filled
self._frameGen = [None for lane in range(numLane)]
# Create the stream interface
for lane in range(numLane):
# Create the frame generator
self._frameGen[lane] = MyCustomMaster()
# Connect the frame generator
pr.streamConnect(self._frameGen[lane], self._pgp[lane][1])
# Create a command to execute the frame generator
self.add(
pr.BaseCommand(
name=f'GenFrame[{lane}]',
function=lambda cmd, lane=lane: self._frameGen[lane].
myFrameGen(),
))
self.add(
pr.LocalVariable(
name='RunState',
description=
'Run state status, which is controlled by the StopRun() and StartRun() commands',
mode='RO',
value=False,
))
@self.command(
description='Stops the triggers and blows off data in the pipeline'
)
def StopRun():
print('ClinkDev.StopRun() executed')
# Get devices
trigChDev = self.find(typ=timingCore.EvrV2ChannelReg)
# Turn off the triggering
for devPtr in trigChDev:
devPtr.EnableReg.set(False)
# Update the run state status variable
self.RunState.set(False)
@self.command(
description=
'starts the triggers and allow steams to flow to DMA engine')
def StartRun():
print('ClinkDev.StartRun() executed')
# Get devices
trigChDev = self.find(typ=timingCore.EvrV2ChannelReg)
# Reset all counters
self.CountReset()
# Turn on the triggering
for devPtr in trigChDev:
devPtr.EnableReg.set(True)
# Update the run state status variable
self.RunState.set(True)
# Start the system
self.start(
pollEn=self._pollEn,
initRead=self._initRead,
timeout=self._timeout,
)
# Hide all the "enable" variables
for enableList in self.find(typ=pr.EnableVariable):
# Hide by default
enableList.hidden = True
# Check if simulation
if (dev == 'sim'):
# Disable the PGP PHY device (speed up the simulation)
self.Hardware.enable.set(False)
self.Hardware.hidden = True
# Bypass the time AXIS channel
eventDev = self.find(typ=batcher.AxiStreamBatcherEventBuilder)
for dev in eventDev:
dev.Bypass.set(0x1)
else:
# Read all the variables
self.ReadAll()
# Check for min. PCIe FW version
fwVersion = self.Hardware.AxiPcieCore.AxiVersion.FpgaVersion.get()
if (fwVersion < self.minPcieVersion):
errMsg = f"""
PCIe.AxiVersion.FpgaVersion = {fwVersion:#04x} < {self.minPcieVersion:#04x}
Please update PCIe firmware using software/scripts/updatePcieFpga.py
"""
click.secho(errMsg, bg='red')
raise ValueError(errMsg)
# Check for min. FEB FW version
for lane in range(numLane):
# Unhide the because dependent on PGP link status
self.ClinkFeb[lane].enable.hidden = False
# Check for PGP link up
if (self.Hardware.PgpMon[lane].RxRemLinkReady.get() != 0):
# Expand for the GUI
self.ClinkFeb[lane]._expand = True
self.ClinkFeb[lane].ClinkTop._expand = True
self.ClinkFeb[lane].TrigCtrl[0]._expand = True
self.ClinkFeb[lane].TrigCtrl[1]._expand = True
if camType[1] is None:
self.ClinkFeb[lane].ClinkTop.Ch[1]._expand = False
self.ClinkFeb[lane].TrigCtrl[1]._expand = False
# Check for min. FW version
fwVersion = self.ClinkFeb[lane].AxiVersion.FpgaVersion.get(
)
if (fwVersion < self.minFebVersion):
errMsg = f"""
Fpga[lane={lane}].AxiVersion.FpgaVersion = {fwVersion:#04x} < {self.minFebVersion:#04x}
Please update Fpga[{lane}] at Lane={lane} firmware using software/scripts/updateFeb.py
"""
click.secho(errMsg, bg='red')
raise ValueError(errMsg)
else:
self.Application.AppLane[lane]._expand = False
# Startup procedures for OPA1000
uartDev = self.find(typ=cl.UartOpal1000)
for dev in uartDev:
pass
# Startup procedures for Piranha4
uartDev = self.find(typ=cl.UartPiranha4)
for dev in uartDev:
dev.SendEscape()
dev.SPF.setDisp('0')
dev.GCP()
# Startup procedures for Up900cl12b
uartDev = self.find(typ=cl.UartUp900cl12b)
for dev in uartDev:
clCh = self.find(typ=cl.ClinkChannel)
for clChDev in clCh:
clChDev.SerThrottle.set(30000)
dev.AM()
dev.SM.set('f')
dev.RP()
# Load the configurations
if self.defaultFile is not None:
print(f'Loading {self.defaultFile} Configuration File...')
self.LoadConfig(self.defaultFile)
def __init__(self,
name="MyRoot",
description="my root container",
**kwargs):
super().__init__(name=name, description=description, **kwargs)
#################################################################
# DataDev PCIe Card
if (args.type == 'datadev'):
self.vc0Srp = rogue.hardware.axi.AxiStreamDma(
args.dev, (args.lane * 0x100) + 0, True)
self.vc1Prbs = rogue.hardware.axi.AxiStreamDma(
args.dev, (args.lane * 0x100) + 1, True)
# self.vc1Prbs.setZeroCopyEn(False)
# RUDP Ethernet
elif (args.type == 'eth'):
# Create the ETH interface @ IP Address = args.dev
self.rudp = pr.protocols.UdpRssiPack(
host=args.ip,
port=8192,
packVer=args.packVer,
jumbo=True,
expand=False,
)
self.add(self.rudp)
# Map the AxiStream.TDEST
self.vc0Srp = self.rudp.application(0)
# AxiStream.tDest = 0x0
self.vc1Prbs = self.rudp.application(1)
# AxiStream.tDest = 0x1
# self.vc1Prbs.setZeroCopyEn(False)
# Legacy PGP PCIe Card
elif (args.type == 'pgp'):
self.vc0Srp = rogue.hardware.pgp.PgpCard(args.dev, args.lane,
0) # Registers
self.vc1Prbs = rogue.hardware.pgp.PgpCard(args.dev, args.lane,
1) # Data
# self.vc1Prbs.setZeroCopyEn(False)
# Undefined device type
else:
raise ValueError("Invalid type (%s)" % (args.type))
#################################################################
# Connect VC0 to SRPv3
self.srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.vc0Srp, self.srp)
if args.enPrbs:
# Connect VC1 to FW TX PRBS
self.prbsRx = pyrogue.utilities.prbs.PrbsRx(name='PrbsRx',
width=128,
expand=False)
pyrogue.streamConnect(self.vc1Prbs, self.prbsRx)
self.add(self.prbsRx)
# Connect VC1 to FW RX PRBS
self.prbTx = pyrogue.utilities.prbs.PrbsTx(name="PrbsTx",
width=128,
expand=False)
pyrogue.streamConnect(self.prbTx, self.vc1Prbs)
self.add(self.prbTx)
else:
pyrogue.streamConnect(self.vc1Prbs, self.vc1Prbs)
# Add registers
self.add(
devBoard.Fpga(
memBase=self.srp,
commType=args.type,
fpgaType=args.fpgaType,
))
def __init__(self,
name="Top",
description="Container for HPS BLD",
ipAddr='10.0.1.101',
memBase=0,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
################################################################################################################
# UDP_SRV_XVC_IDX_C => 2542, -- Xilinx XVC
# UDP_SRV_SRPV0_IDX_C => 8192, -- Legacy SRPv0 register access (still used for remote FPGA reprogramming)
# UDP_SRV_RSSI0_IDX_C => 8193, -- Legacy Non-interleaved RSSI for Register access and ASYNC messages
# UDP_SRV_RSSI1_IDX_C => 8194, -- Legacy Non-interleaved RSSI for bulk data transfer
# UDP_SRV_BP_MGS_IDX_C => 8195, -- Backplane Messaging
# UDP_SRV_TIMING_IDX_C => 8197, -- Timing ASYNC Messaging
# UDP_SRV_RSSI_ILEAVE_IDX_C => 8198); -- Interleaved RSSI
################################################################################################################
# Create SRP/ASYNC_MSG interface
if False:
# UDP only
self.udp = rogue.protocols.udp.Client(ipAddr, 8192, 0)
# Connect the SRPv0 to RAW UDP
self.srp = rogue.protocols.srp.SrpV0()
pyrogue.streamConnectBiDir(self.srp, self.udp)
if True:
self.rudp = pyrogue.protocols.UdpRssiPack(name='rudpReg',
host=ipAddr,
port=8193,
packVer=1,
jumbo=False)
# Connect the SRPv3 to tDest = 0x0
self.srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.srp, self.rudp.application(dest=0x0))
# Create stream interface
#self.stream = pr.protocols.UdpRssiPack( name='rudpData', host=ipAddr, port=8194, packVer = 1, jumbo = False)
######################################################################
# Add devices
self.add(
axi.AxiVersion(
memBase=self.srp,
offset=0x00000000,
expand=False,
))
self.add(
xil.AxiSysMonUltraScale(memBase=self.srp,
offset=0x01000000,
expand=False))
self.add(
micron.AxiMicronN25Q(
memBase=self.srp,
name="MicronN25Q",
offset=0x02000000,
addrMode=True,
expand=False,
hidden=True,
))
self.add(microchip.AxiSy56040(
memBase = self.srp,
offset = 0x03000000,
expand = False,
description = "\n\
Timing Crossbar: https://confluence.slac.stanford.edu/x/m4H7D \n\
-----------------------------------------------------------------\n\
OutputConfig[0] = 0x0: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN0\n\
OutputConfig[0] = 0x1: Connects RTM_TIMING_OUT0 to FPGA_TIMING_IN\n\
OutputConfig[0] = 0x2: Connects RTM_TIMING_OUT0 to BP_TIMING_IN\n\
OutputConfig[0] = 0x3: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[1] = 0x0: Connects FPGA_TIMING_OUT to RTM_TIMING_IN0\n\
OutputConfig[1] = 0x1: Connects FPGA_TIMING_OUT to FPGA_TIMING_IN\n\
OutputConfig[1] = 0x2: Connects FPGA_TIMING_OUT to BP_TIMING_IN\n\
OutputConfig[1] = 0x3: Connects FPGA_TIMING_OUT to RTM_TIMING_IN1 \n\
-----------------------------------------------------------------\n\
OutputConfig[2] = 0x0: Connects Backplane DIST0 to RTM_TIMING_IN0\n\
OutputConfig[2] = 0x1: Connects Backplane DIST0 to FPGA_TIMING_IN\n\
OutputConfig[2] = 0x2: Connects Backplane DIST0 to BP_TIMING_IN\n\
OutputConfig[2] = 0x3: Connects Backplane DIST0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[3] = 0x0: Connects Backplane DIST1 to RTM_TIMING_IN0\n\
OutputConfig[3] = 0x1: Connects Backplane DIST1 to FPGA_TIMING_IN\n\
OutputConfig[3] = 0x2: Connects Backplane DIST1 to BP_TIMING_IN\n\
OutputConfig[3] = 0x3: Connects Backplane DIST1 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n"\
))
# self.add(ti.AxiCdcm6208(
# memBase = self.srp,
# offset = 0x05000000,
# expand = False,
# ))
self.add(
timing.TimingFrameRx(
memBase=self.srp,
name='UsTiming',
offset=0x08000000,
))
self.add(
hps.AmcCarrierBsa(
memBase=self.srp,
name='AmcCarrierBsa',
offset=0x09000000,
))
def __init__(self,
name="Top",
description="Container for XPM",
ipAddr='10.0.1.101',
memBase=0,
fidPrescale=200,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
################################################################################################################
# UDP_SRV_XVC_IDX_C => 2542, -- Xilinx XVC
# UDP_SRV_SRPV0_IDX_C => 8192, -- Legacy SRPv0 register access (still used for remote FPGA reprogramming)
# UDP_SRV_RSSI0_IDX_C => 8193, -- Legacy Non-interleaved RSSI for Register access and ASYNC messages
# UDP_SRV_RSSI1_IDX_C => 8194, -- Legacy Non-interleaved RSSI for bulk data transfer
# UDP_SRV_BP_MGS_IDX_C => 8195, -- Backplane Messaging
# UDP_SRV_TIMING_IDX_C => 8197, -- Timing ASYNC Messaging
# UDP_SRV_RSSI_ILEAVE_IDX_C => 8198); -- Interleaved RSSI
################################################################################################################
# Create SRP/ASYNC_MSG interface
if False:
# UDP only
self.udp = rogue.protocols.udp.Client(ipAddr, 8192, 0)
# Connect the SRPv0 to RAW UDP
self.srp = rogue.protocols.srp.SrpV0()
pyrogue.streamConnectBiDir(self.srp, self.udp)
if True:
self.rudp = pyrogue.protocols.UdpRssiPack(name='rudpReg',
host=ipAddr,
port=8193,
packVer=1,
jumbo=False)
# Connect the SRPv3 to tDest = 0x0
self.srp = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.srp, self.rudp.application(dest=0x0))
# Create stream interface
self.stream = pr.protocols.UdpRssiPack(name='rudpData',
host=ipAddr,
port=8194,
packVer=1,
jumbo=False)
######################################################################
# Add devices
self.add(
axi.AxiVersion(
memBase=self.srp,
offset=0x00000000,
expand=False,
))
self.add(
xil.AxiSysMonUltraScale(memBase=self.srp,
offset=0x01000000,
expand=False))
self.add(
micron.AxiMicronN25Q(
memBase=self.srp,
name="MicronN25Q",
offset=0x2000000,
addrMode=True,
expand=False,
hidden=True,
))
self.add(microchip.AxiSy56040(
memBase = self.srp,
offset = 0x03000000,
expand = False,
description = "\n\
Timing Crossbar: https://confluence.slac.stanford.edu/x/m4H7D \n\
-----------------------------------------------------------------\n\
OutputConfig[0] = 0x0: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN0\n\
OutputConfig[0] = 0x1: Connects RTM_TIMING_OUT0 to FPGA_TIMING_IN\n\
OutputConfig[0] = 0x2: Connects RTM_TIMING_OUT0 to BP_TIMING_IN\n\
OutputConfig[0] = 0x3: Connects RTM_TIMING_OUT0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[1] = 0x0: Connects FPGA_TIMING_OUT to RTM_TIMING_IN0\n\
OutputConfig[1] = 0x1: Connects FPGA_TIMING_OUT to FPGA_TIMING_IN\n\
OutputConfig[1] = 0x2: Connects FPGA_TIMING_OUT to BP_TIMING_IN\n\
OutputConfig[1] = 0x3: Connects FPGA_TIMING_OUT to RTM_TIMING_IN1 \n\
-----------------------------------------------------------------\n\
OutputConfig[2] = 0x0: Connects Backplane DIST0 to RTM_TIMING_IN0\n\
OutputConfig[2] = 0x1: Connects Backplane DIST0 to FPGA_TIMING_IN\n\
OutputConfig[2] = 0x2: Connects Backplane DIST0 to BP_TIMING_IN\n\
OutputConfig[2] = 0x3: Connects Backplane DIST0 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n\
OutputConfig[3] = 0x0: Connects Backplane DIST1 to RTM_TIMING_IN0\n\
OutputConfig[3] = 0x1: Connects Backplane DIST1 to FPGA_TIMING_IN\n\
OutputConfig[3] = 0x2: Connects Backplane DIST1 to BP_TIMING_IN\n\
OutputConfig[3] = 0x3: Connects Backplane DIST1 to RTM_TIMING_IN1\n\
-----------------------------------------------------------------\n"\
))
self.add(
ti.AxiCdcm6208(
memBase=self.srp,
offset=0x05000000,
expand=False,
))
self.add(
xpm.TimingFrameRx(
memBase=self.srp,
name='UsTiming',
offset=0x08000000,
))
self.add(
xpm.TimingFrameRx(
memBase=self.srp,
name='CuTiming',
offset=0x08400000,
))
self.add(
xpm.CuGenerator(
memBase=self.srp,
name='CuGenerator',
offset=0x08800000,
))
for i in range(len(Top.mmcmParms)):
self.add(
xpm.MmcmPhaseLock(
memBase=self.srp,
name=Top.mmcmParms[i][0],
offset=Top.mmcmParms[i][1],
))
hsrParms = [['HSRep0', 0x09000000], ['HSRep1', 0x09010000],
['HSRep2', 0x09020000], ['HSRep3', 0x09030000],
['HSRep4', 0x09040000], ['HSRep5', 0x09050000]]
for i in range(len(hsrParms)):
self.add(
xpm.Ds125br401(
memBase=self.srp,
name=hsrParms[i][0],
offset=hsrParms[i][1],
))
self.amcs = []
for i in range(2):
amc = xpm.MpsSfpAmc(
memBase=self.srp,
name='Amc%d' % i,
offset=0x09000000 + (i + 1) * 0x100000,
)
self.add(amc)
self.amcs.append(amc)
# self.add(timing.GthRxAlignCheck(
self.add(
xpm.GthRxAlignCheck(
memBase=self.srp,
name='UsGthRxAlign',
offset=0x0b000000,
))
# self.add(timing.GthRxAlignCheck(
self.add(
xpm.GthRxAlignCheck(
memBase=self.srp,
name='CuGthRxAlign',
offset=0x0c000000,
))
self.add(
xpm.XpmApp(
memBase=self.srp,
name='XpmApp',
offset=0x80000000,
fidPrescale=fidPrescale,
))
self.add(
AxiLiteRingBuffer(
memBase=self.srp,
name='AxiLiteRingBuffer',
datawidth=16,
offset=0x80010000,
))
self.add(
xpm.XpmSequenceEngine(
memBase=self.srp,
name='SeqEng_0',
offset=0x80020000,
))
# self.add(xpm.CuPhase(
# memBase = self.srp,
# name = 'CuPhase',
# offset = 0x80050000,
# ))
self.add(
xpm.XpmPhase(
memBase=self.srp,
name='CuToScPhase',
offset=0x80050000,
))
def __init__(self,
name='Top',
description='Container for FEB FPGA',
ip=['10.0.0.1'],
pollEn=True,
initRead=True,
configProm=False,
advanceUser=False,
refClkSel=['IntClk'],
loadYaml=True,
userYaml=[''],
defaultFile='config/defaults.yml',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# Set the min. firmware Version support by the software
self.minFpgaVersion = 0x20000060
# Enable Init after config
self.InitAfterConfig._default = True
# Cache the parameters
self.advanceUser = advanceUser
self.configProm = configProm
self.ip = ip
self.numEthDev = len(ip) if (ip[0] != 'simulation') else 1
self._timeout = 1.0 if (ip[0] != 'simulation') else 100.0
self._pollEn = pollEn if (ip[0] != 'simulation') else False
self._initRead = initRead if (ip[0] != 'simulation') else False
self.usrLoadYaml = loadYaml
self.userYaml = userYaml
self.defaultFile = defaultFile
self.pllConfig = [None for i in range(self.numEthDev)]
# Check if missing refClkSel configuration
if (len(refClkSel) < len(ip)):
errMsg = f'len(refClkSel) = {len(refClkSel)} < len(ip) = {len(ip)}.\nMake sure to define a refClkSel for each IP address'
click.secho(errMsg, bg='red')
raise ValueError(errMsg)
# Set the path of the PLL configuration file
for i in range(self.numEthDev):
if (refClkSel[i] == 'IntClk'):
self.pllConfig[
i] = 'config/pll-config/Si5345-RevD-Registers-IntClk.csv'
elif (refClkSel[i] == 'ExtSmaClk'):
self.pllConfig[
i] = 'config/pll-config/Si5345-RevD-Registers-ExtSmaClk.csv'
elif (refClkSel[i] == 'ExtLemoClk'):
self.pllConfig[
i] = 'config/pll-config/Si5345-RevD-Registers-ExtLemoClk.csv'
else:
errMsg = f'refClkSel[{i}] argument must be either [IntClk,ExtSmaClk,ExtLemoClk]'
click.secho(errMsg, bg='red')
raise ValueError(errMsg)
# File writer
self.dataWriter = pr.utilities.fileio.StreamWriter()
self.add(self.dataWriter)
# Create arrays to be filled
self.rudp = [None for i in range(self.numEthDev)]
self.srpStream = [None for i in range(self.numEthDev)]
self.dataStream = [None for i in range(self.numEthDev)]
self.semStream = [None for i in range(self.numEthDev)]
self.memMap = [None for i in range(self.numEthDev)]
# SEM monitor streams
self.semDataWriter = SemAsciiFileWriter()
# Loop through the devices
for i in range(self.numEthDev):
######################################################################
if (self.ip[0] == 'simulation'):
self.srpStream[i] = rogue.interfaces.stream.TcpClient(
'localhost', 9000)
self.dataStream[i] = rogue.interfaces.stream.TcpClient(
'localhost', 9002)
else:
self.rudp[i] = pr.protocols.UdpRssiPack(host=ip[i],
port=8192,
packVer=2,
jumbo=False)
self.srpStream[i] = self.rudp[i].application(0)
self.dataStream[i] = self.rudp[i].application(1)
self.semStream[i] = self.rudp[i].application(2)
######################################################################
# Connect the SRPv3 to PGPv3.VC[0]
self.memMap[i] = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.memMap[i], self.srpStream[i])
# Check if not PROM loading
if not self.configProm:
# Connect data stream to file as channel to dataStream
pr.streamConnect(self.dataStream[i],
self.dataWriter.getChannel(i))
# Connect to the SEM monitor streams and file writer
pr.streamConnect(self.semStream[i], self.semDataWriter)
pr.streamTap(self.semStream[i],
self.dataWriter.getChannel(i + 128))
######################################################################
# Add devices
self.add(
common.Fpga(
name=f'Fpga[{i}]',
memBase=self.memMap[i],
offset=0x00000000,
configProm=self.configProm,
advanceUser=self.advanceUser,
expand=True,
))
######################################################################
self.add(
pr.LocalVariable(
name="LiveDisplayRst",
mode="RW",
value=0x0,
hidden=True,
))
@self.command()
def LiveDisplayReset(arg):
print('LiveDisplayReset()')
self.LiveDisplayRst.set(1)
for reset in self.reset_list:
reset()
self.LiveDisplayRst.set(0)
@self.command(
description=
'This command is intended to be executed before self.dataWriter is closed'
)
def StopRun(arg):
click.secho('StopRun()', bg='yellow')
# Stop the Master First
for i in range(self.numEthDev):
if self.Fpga[i].Asic.Trig.TrigTypeSel.getDisp() == 'Master':
self.Fpga[i].Asic.Trig.EnableReadout.set(0x0)
click.secho(
f'self.Fpga[{i}].Asic.Trig.EnableReadout.set(0x0)',
bg='bright_magenta')
# Stop the Slave after the Master
for i in range(self.numEthDev):
if self.Fpga[i].Asic.Trig.TrigTypeSel.getDisp() == 'Slave':
self.Fpga[i].Asic.Trig.EnableReadout.set(0x0)
click.secho(
f'self.Fpga[{i}].Asic.Trig.EnableReadout.set(0x0)',
bg='magenta')
@self.command(
description=
'This command is intended to be executed after self.dataWriter is opened'
)
def StartRun(arg):
click.secho('StartRun()', bg='blue')
# Reset the sequence and trigger counters
for i in range(self.numEthDev):
self.Fpga[i].Asic.Trig.countReset()
self.Fpga[i].Asic.Readout.SeqCntRst()
# Start the Slave First
for i in range(self.numEthDev):
if self.Fpga[i].Asic.Trig.TrigTypeSel.getDisp() == 'Slave':
self.Fpga[i].Asic.Trig.EnableReadout.set(0x1)
click.secho(
f'self.Fpga[{i}].Asic.Trig.EnableReadout.set(0x1)',
bg='magenta')
# Start the Master after the Slave
for i in range(self.numEthDev):
if self.Fpga[i].Asic.Trig.TrigTypeSel.getDisp() == 'Master':
self.Fpga[i].Asic.Trig.EnableReadout.set(0x1)
click.secho(
f'self.Fpga[{i}].Asic.Trig.EnableReadout.set(0x1)',
bg='bright_magenta')
@self.command(
description=
'This command is intended to be executed after self.dataWriter is opened'
)
def ResumeRun(arg):
click.secho('ResumeRun()', bg='blue')
# Start the Slave First
for i in range(self.numEthDev):
if self.Fpga[i].Asic.Trig.TrigTypeSel.getDisp() == 'Slave':
self.Fpga[i].Asic.Trig.EnableReadout.set(0x1)
click.secho(
f'self.Fpga[{i}].Asic.Trig.EnableReadout.set(0x1)',
bg='magenta')
# Start the Master after the Slave
for i in range(self.numEthDev):
if self.Fpga[i].Asic.Trig.TrigTypeSel.getDisp() == 'Master':
self.Fpga[i].Asic.Trig.EnableReadout.set(0x1)
click.secho(
f'self.Fpga[{i}].Asic.Trig.EnableReadout.set(0x1)',
bg='bright_magenta')
######################################################################
# Start the system
self.start(
pollEn=self._pollEn,
initRead=self._initRead,
timeout=self._timeout,
)
def data_path(ver, jumbo):
print("Testing ver={} jumbo={}".format(ver, jumbo))
# UDP Server
serv = rogue.protocols.udp.Server(0, jumbo)
port = serv.getPort()
# UDP Client
client = rogue.protocols.udp.Client("127.0.0.1", port, jumbo)
# RSSI
sRssi = rogue.protocols.rssi.Server(serv.maxPayload())
cRssi = rogue.protocols.rssi.Client(client.maxPayload())
# Packetizer
if ver == 1:
sPack = rogue.protocols.packetizer.Core(True)
cPack = rogue.protocols.packetizer.Core(True)
else:
sPack = rogue.protocols.packetizer.CoreV2(True, True, True)
cPack = rogue.protocols.packetizer.CoreV2(True, True, True)
# PRBS
prbsTx = rogue.utilities.Prbs()
prbsRx = rogue.utilities.Prbs()
# Client stream
pyrogue.streamConnect(prbsTx, cPack.application(0))
pyrogue.streamConnectBiDir(cRssi.application(), cPack.transport())
pyrogue.streamConnectBiDir(client, cRssi.transport())
# Server stream
pyrogue.streamConnectBiDir(serv, sRssi.transport())
pyrogue.streamConnectBiDir(sRssi.application(), sPack.transport())
pyrogue.streamConnect(sPack.application(0), prbsRx)
# Start RSSI
sRssi.start()
cRssi.start()
# Wait for connection
cnt = 0
print("Waiting for RSSI connection")
while not cRssi.getOpen():
time.sleep(1)
cnt += 1
if cnt == 10:
cRssi.stop()
sRssi.stop()
raise AssertionError('RSSI timeout error. Ver={} Jumbo={}'.format(
ver, jumbo))
print("Generating Frames")
for _ in range(FrameCount):
prbsTx.genFrame(FrameSize)
time.sleep(1)
# Stop connection
print("Closing Link")
cRssi.stop()
sRssi.stop()
if prbsRx.getRxCount() != FrameCount:
raise AssertionError(
'Frame count error. Ver={} Jumbo={} Got = {} expected = {}'.format(
ver, jumbo, prbsRx.getRxCount(), FrameCount))
if prbsRx.getRxErrors() != 0:
raise AssertionError(
'PRBS Frame errors detected! Ver={} Jumbo={}'.format(ver, jumbo))
print("Done testing ver={} jumbo={}".format(ver, jumbo))
def __eq__(self, other):
pyrogue.streamConnectBiDir(other, self)
)
# Get the arguments
args = parser.parse_args()
# Set base
base = pr.Root(name='base',description='')
# Create srp interface
srp = rogue.protocols.srp.SrpV3()
# UDP only
udp = rogue.protocols.udp.Client( args.ip, 8192, 1500 )
# Connect the SRPv3 to UDP
pr.streamConnectBiDir( srp, udp )
# Add Base Device
base.add(board.Core(
memBase = srp,
offset = 0x00000000,
))
# Start the system
base.start(pollEn=False)
# Create useful pointers
AxiVersion = base.Core.AxiVersion
MicronN25Q = base.Core.AxiMicronN25Q
# Token write to scratchpad to RAW UDP connection
def __init__(self,
name="Top",
description="Container for FEB FPGA",
dev='/dev/datadev_0',
hwType='pcie',
ip='10.0.0.1',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# File writer
dataWriter = pr.utilities.fileio.StreamWriter()
self.add(dataWriter)
######################################################################
if (hwType == 'hsio-dtm') or (hwType == 'rce-dpm'):
# Create the mmap interface
rceMap = rogue.hardware.axi.AxiMemMap('/dev/rce_memmap')
# Add RCE version device
self.add(rceg3.RceVersion(
memBase=rceMap,
expand=False,
))
# Add PGPv3 to the FEB
self.add(
pgp.Pgp3AxiL(
name='Pgp3Mon',
memBase=rceMap,
offset=0xA0000000,
numVc=1,
writeEn=True,
expand=False,
))
if (hwType == 'hsio-dtm'):
# Add PGPv2b to the HSIO FPGA
self.add(
pgp.Pgp2bAxi(
name='Pgp2bMon',
memBase=rceMap,
offset=0xA1000000,
expand=False,
))
# Connect the SRPv0 to PGPv2b.VC[1]
pgp2bVc1 = rogue.hardware.axi.AxiStreamDma(
'/dev/axi_stream_dma_0', 1, True)
srpV0 = rogue.protocols.srp.SrpV0()
pr.streamConnectBiDir(srpV0, pgp2bVc1)
if (hwType == 'pcie'):
axiMemMap = rogue.hardware.axi.AxiMemMap(dev)
self.add(
pcie.AxiPcieCore(
memBase=axiMemMap,
offset=0x00000000,
expand=False,
))
# for i in range(8):
# self.add(pgp.Pgp3AxiL(
# memBase = axiMemMap,
# name = ('Pgp3Mon[%d]' % i),
# offset = (0x00800000 + i*0x10000),
# numVc = 16,
# writeEn = True,
# expand = False,
# ))
######################################################################
# Create an empty stream arrays
configStream = [None] * 4
dataStream = [None] * 4
########################################################################################################################
# https://github.com/slaclab/rogue/blob/master/include/rogue/hardware/axi/AxiStreamDma.h
# static boost::shared_ptr<rogue::hardware::axi::AxiStreamDma> create (std::string path, uint32_t dest, bool ssiEnable);
########################################################################################################################
######################################################################
# PGPv3.[VC=0] = FEB SRPv3 Register Access
# PGPv3.[VC=1] = RD53[DPORT=0] Streaming ASIC Configuration Interface
# PGPv3.[VC=2] = RD53[DPORT=1] Streaming ASIC Configuration Interface
# PGPv3.[VC=3] = RD53[DPORT=2] Streaming ASIC Configuration Interface
# PGPv3.[VC=4] = RD53[DPORT=3] Streaming ASIC Configuration Interface
# PGPv3.[VC=5] = RD53[DPORT=0] Streaming Data Interface
# PGPv3.[VC=6] = RD53[DPORT=1] Streaming Data Interface
# PGPv3.[VC=7] = RD53[DPORT=2] Streaming Data Interface
# PGPv3.[VC=8] = RD53[DPORT=3] Streaming Data Interface
######################################################################
if (hwType == 'simulation'):
srpStream = pr.interfaces.simulation.StreamSim(host='localhost',
dest=0,
uid=12,
ssi=True)
for i in range(4):
configStream[i] = pr.interfaces.simulation.StreamSim(
host='localhost', dest=1 + i, uid=12, ssi=True)
dataStream[i] = pr.interfaces.simulation.StreamSim(
host='localhost', dest=5 + i, uid=12, ssi=True)
elif (hwType == 'eth'):
rudp = pr.protocols.UdpRssiPack(host=ip, port=8192, packVer=2)
srpStream = rudp.application(0)
for i in range(4):
configStream[i] = rudp.application(1 + i)
dataStream[i] = rudp.application(5 + i)
else:
srpStream = rogue.hardware.axi.AxiStreamDma(dev, 0, True)
for i in range(4):
configStream[i] = rogue.hardware.axi.AxiStreamDma(
dev, 1 + i, True)
dataStream[i] = rogue.hardware.axi.AxiStreamDma(
dev, 5 + i, True)
######################################################################
# Connect the SRPv3 to PGPv3.VC[0]
memMap = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(memMap, srpStream)
for i in range(4):
# Add data stream to file as channel [i] to dataStream[i]
pr.streamConnect(dataStream[i], dataWriter.getChannel(i))
######################################################################
# Add devices
self.add(
axiVer.AxiVersion(
name='AxiVersion',
memBase=memMap,
offset=0x00000000,
expand=False,
))
self.add(
xil.Xadc(
name='Xadc',
memBase=memMap,
offset=0x00010000,
expand=False,
))
self.add(
prom.AxiMicronP30(
name='AxiMicronP30',
memBase=memMap,
offset=0x00020000,
hidden=True, # Hidden in GUI because indented for scripting
))
self.add(
common.SysReg(
name='SysReg',
description=
'This device contains system level configuration and status registers',
memBase=memMap,
offset=0x00030000,
expand=False,
))
self.add(
common.Ntc(
name='Rd53Ntc',
description=
'This device contains the four NTC MAX6682 readout modules',
memBase=memMap,
offset=0x00040000,
expand=False,
))
self.add(
nxp.Sa56004x(
name='BoardTemp',
description=
'This device monitors the board temperature and FPGA junction temperature',
memBase=memMap,
offset=0x00050000,
expand=False,
))
self.add(
linear.Ltc4151(
name='BoardPwr',
description=
'This device monitors the board power, input voltage and input current',
memBase=memMap,
offset=0x00050400,
senseRes=20.E-3, # Units of Ohms
expand=False,
))
for i in range(4):
self.add(
common.RxPhyMon(
name=('RxPhyMon[%d]' % i),
memBase=memMap,
offset=(0x01000000 * (i + 1) + 0x00100000),
expand=False,
))
self.add(
common.Timing(
name='Timing',
description=
'This device monitors the TLU and timing/trigger emulator',
memBase=memMap,
offset=0x05000000,
expand=False,
))
def __init__(
self,
name='TimeToolDev',
description='Container for TimeTool Dev',
dataDebug=False,
dev='/dev/datadev_0', # path to PCIe device
version3=False, # true = PGPv3, false = PGP2b
pollEn=True, # Enable automatic polling registers
initRead=True, # Read all registers at start of the system
numLane=1, # Number of PGP lanes
**kwargs):
super().__init__(name=name,
description=description,
dev=dev,
version3=version3,
pollEn=pollEn,
initRead=initRead,
numLane=numLane,
**kwargs)
# Check if not doing simulation
if (dev != 'sim'):
# Create arrays to be filled
self._srp = [None for lane in range(numLane)]
# Create the stream interface
for lane in range(numLane):
# SRP
self._srp[lane] = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self._dma[lane][0], self._srp[lane])
# CameraLink Feb Board
self.add(
feb.ClinkFeb(
name=(f'ClinkFeb[{lane}]'),
memBase=self._srp[lane],
serial=[self._dma[lane][2], None],
camType=['Piranha4', None],
version3=version3,
enableDeps=[
self.Hardware.PgpMon[lane].RxRemLinkReady
], # Only allow access if the PGP link is established
# expand = False,
))
# Else doing Rogue VCS simulation
else:
# Create arrays to be filled
self._frameGen = [None for lane in range(numLane)]
# Create the stream interface
for lane in range(numLane):
# Create the frame generator
self._frameGen[lane] = MyCustomMaster()
# Connect the frame generator
pr.streamConnect(self._frameGen[lane], self._pgp[lane][1])
# Create a command to execute the frame generator
self.add(
pr.BaseCommand(
name=f'GenFrame[{lane}]',
function=lambda cmd: self._frameGen[lane].myFrameGen(),
))
# Create arrays to be filled
self._dbg = [None for lane in range(numLane)]
# Create the stream interface
for lane in range(numLane):
# Debug slave
if dataDebug:
self._dbg[lane] = TimeToolRx(expand=False)
pr.streamTap(self._dma[lane][1], self._dbg[lane])
self.add(self._dbg)
# Time tool application
self.add(
timeTool.Application(
memBase=self._memMap,
offset=0x00C00000,
numLane=numLane,
))
# Start the system
self.start(
pollEn=self._pollEn,
initRead=self._initRead,
timeout=self._timeout,
)
# Check if not simulation
if (dev != 'sim'):
# Read all the variables
self.ReadAll()
# Some initialization after starting root
for lane in range(numLane):
self.ClinkFeb[lane].ClinkTop.Ch[0].BaudRate.set(9600)
self.ClinkFeb[lane].ClinkTop.Ch[0].SerThrottle.set(10000)
self.ClinkFeb[lane].ClinkTop.Ch[0].LinkMode.setDisp('Full')
self.ClinkFeb[lane].ClinkTop.Ch[0].DataMode.setDisp('8Bit')
self.ClinkFeb[lane].ClinkTop.Ch[0].FrameMode.setDisp('Line')
self.ClinkFeb[lane].ClinkTop.Ch[0].TapCount.set(8)
self.ClinkFeb[lane].ClinkTop.Ch[0].UartPiranha4.SendEscape()
self.ClinkFeb[lane].ClinkTop.Ch[0].UartPiranha4.SPF.setDisp(
'0')
self.ClinkFeb[lane].ClinkTop.Ch[0].UartPiranha4.GCP()
else:
# Disable the PGP PHY device (speed up the simulation)
self.Hardware.enable.set(False)
self.Hardware.hidden = True
# Bypass the time AXIS channel
eventDev = self.find(typ=batcher.AxiStreamBatcherEventBuilder)
for dev in eventDev:
dev.Bypass.set(0x1)
def connectPgp2bSim(pgpA, pgpB):
for a, b in zip(pgpA.vc, pgpB.vc):
pyrogue.streamConnectBiDir(a, b)
pgpA.sb.setRecvCb(pgpB.sb.send)
pgpB.sb.setRecvCb(pgpA.sb.send)
def __init__(self,
*,
ip_addr="",
config_file=None,
epics_prefix="EpicsPrefix",
polling_en=True,
pv_dump_file="",
disable_bay0=False,
disable_bay1=False,
enable_pwri2c=False,
txDevice=None,
configure=False,
VariableGroups=None,
server_port=0,
**kwargs):
# Create Interleaved RSSI interface
self._stream = pyrogue.protocols.UdpRssiPack(name='rudp',
host=ip_addr,
port=8198,
packVer=2,
jumbo=True)
# Create the SRP Engine
self._srp = rogue.protocols.srp.SrpV3()
pyrogue.streamConnectBiDir(self._srp,
self._stream.application(dest=0x0))
# Instantiate Fpga top level
# In order to be backwards compatible for now, also support
# FpgaTopLevel which doesn't have the enablePwrI2C argument.
try:
self._fpga = FpgaTopLevel(memBase=self._srp,
disableBay0=disable_bay0,
disableBay1=disable_bay1,
enablePwrI2C=enable_pwri2c)
except TypeError as e:
print(f"TypeError calling FpgaTopLevel: {e}")
print(
"This FpgaTopLevel does not support the option 'enablePwrI2C'."
)
print("Please use a pyrogue zip file which is up to date.")
print(
"Staring the server without using the 'enablePwrI2C' option.")
self._fpga = FpgaTopLevel(memBase=self._srp,
disableBay0=disable_bay0,
disableBay1=disable_bay1)
# Create ddr stream interfaces for base class
self._ddr_streams = []
# DDR streams. The FpgaTopLevel class will defined a 'stream' interface exposing them.
# We are only using the first 2 channel of each AMC daughter card, i.e. channels 0, 1, 4, 5.
for i in [0, 1, 4, 5]:
self._ddr_streams.append(self._stream.application(0x80 + i))
# Streaming interface stream. It comes over UDP, port 8195, without RSSI,
# so we an UdpReceiver.
self._streaming_stream_int = pysmurf.core.devices.UdpReceiver(
ip_addr=ip_addr, port=8195)
# When Ethernet communication is used, We use a FIFO between the stream data and the receiver:
# Stream -> FIFO -> smurf_processor receiver
self._smurf_processor_fifo = rogue.interfaces.stream.Fifo(
100000, 0, True)
pyrogue.streamConnect(self._streaming_stream_int,
self._smurf_processor_fifo)
# Set streaming variable for base class
self._streaming_stream = self._smurf_processor_fifo
# Setup base class
Common.__init__(self,
config_file=config_file,
epics_prefix=epics_prefix,
polling_en=polling_en,
pv_dump_file=pv_dump_file,
txDevice=txDevice,
configure=configure,
VariableGroups=VariableGroups,
server_port=server_port,
**kwargs)
