def bitfield_update_checker(self, input_width, range_start, range_end, update_width, test_amt=20): def ref(i, s, e, u): mask = ((1 << (e)) - 1) - ((1 << s) - 1) return (i & ~mask) | ((u << s) & mask) inp, inp_vals = utils.an_input_and_vals(input_width, test_vals=test_amt, name='inp') upd, upd_vals = utils.an_input_and_vals(update_width, test_vals=test_amt, name='upd') #inp_vals = [1,1,0,0] #upd_vals = [0x7,0x6,0x7,0x6] out = pyrtl.Output(input_width, "out") bfu_out = pyrtl.bitfield_update(inp, range_start, range_end, upd) self.assertEqual(len(out), len(bfu_out)) # output should have width of input out <<= bfu_out true_result = [ ref(i, range_start, range_end, u) for i, u in zip(inp_vals, upd_vals) ] upd_result = utils.sim_and_ret_out(out, [inp, upd], [inp_vals, upd_vals]) self.assertEqual(upd_result, true_result)
def test_single_output_simulates_correctly(self): i, ivals = utils.an_input_and_vals(4, name='i') j, jvals = utils.an_input_and_vals(4, name='j') o = pyrtl.Output(8, 'o') o <<= i * j pyrtl.direct_connect_outputs() true_result = [x * y for x, y in zip(ivals, jvals)] sim_result = utils.sim_and_ret_out(o, [i, j], [ivals, jvals]) self.assertEqual(true_result, sim_result)
def shift_checker(self, shift_func, ref_func, input_width, shift_width, test_amt=20): inp, inp_vals = utils.an_input_and_vals(input_width, test_vals=test_amt, name='inp') shf, shf_vals = utils.an_input_and_vals(shift_width, test_vals=test_amt, name='shf') out = pyrtl.Output(input_width, "out") shf_out = shift_func(inp, shf) self.assertEqual(len(out), len(shf_out)) # output should have width of input out <<= shf_out true_result = [ref_func(i, s) for i, s in zip(inp_vals, shf_vals)] shift_result = utils.sim_and_ret_out(out, [inp, shf], [inp_vals, shf_vals]) self.assertEqual(shift_result, true_result)
def mux_t_subprocess(self, addr_width, val_width): mux_ins, vals = utils.make_consts(num_wires=2**addr_width, exact_bitwidth=val_width) control, testctrl = utils.an_input_and_vals(addr_width, 40, "mux_ctrl") out = pyrtl.Output(val_width, "mux_out") out <<= pyrtl.corecircuits.mux(control, *mux_ins) true_result = [vals[i] for i in testctrl] mux_result = utils.sim_and_ret_out(out, (control,), (testctrl,)) self.assertEqual(mux_result, true_result)
def test_demux_2(self): in_w, in_vals = utils.an_input_and_vals(1) outs = (pyrtl.Output(name="output_" + str(i)) for i in range(2)) demux_outs = pyrtl.rtllib.muxes._demux_2(in_w) for out_w, demux_out in zip(outs, demux_outs): out_w <<= demux_out traces = utils.sim_and_ret_outws((in_w,), (in_vals,)) for cycle in range(20): for i, out_wire in enumerate(outs): self.assertEqual(in_vals[i] == i, traces[out_wire][cycle])
def test_select_no_pred(self): vals = 12, 27 mux_ins = [pyrtl.Const(x) for x in vals] control, testctrl = utils.an_input_and_vals(1, 40, "sel_ctrl", utils.uniform_dist) out = pyrtl.Output(5, "mux_out") out <<= pyrtl.corecircuits.select(control, mux_ins[1], mux_ins[0]) true_result = [vals[i] for i in testctrl] mux_result = utils.sim_and_ret_out(out, (control,), (testctrl,)) self.assertEqual(mux_result, true_result)
def test_mux_with_default(self): addr_width = 5 val_width = 9 default_val = 170 # arbitrary value under 2**val_width num_defaults = 5 mux_ins, vals = utils.make_consts(num_wires=2**addr_width - num_defaults, exact_bitwidth=val_width, random_dist=utils.uniform_dist) control, testctrl = utils.an_input_and_vals(addr_width, 40, "mux_ctrl", utils.uniform_dist) for i in range(5): vals.append(default_val) out = pyrtl.Output(val_width, "mux_out") out <<= pyrtl.corecircuits.mux(control, *mux_ins, default=pyrtl.Const(default_val)) true_result = [vals[i] for i in testctrl] mux_result = utils.sim_and_ret_out(out, (control,), (testctrl,)) self.assertEqual(mux_result, true_result)